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SMB117 PDF预览

SMB117

更新时间: 2022-12-29 05:19:47
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SUMMIT /
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32页 713K
描述
High-power, Four-channel Programmable DC-DC System Power Managers

SMB117 数据手册

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SMB113A/B/SMB117/A  
Preliminary Information  
PIN DESCRIPTION  
Pin Number  
Pin Type  
Pin Name  
Pin Description  
The HSDRV_CH0 (Channel 0 High-side Driver) pin is the upper  
switching node of the channel 0 synchronous step-down buck  
controller. Attach to the gate of p-channel MOSFET. A delay  
exists between the assertion of HSDRV_CH0 and assertion of  
LSDRV_CH0 to prevent excessive current flow during switching.  
1
OUT  
HSDRV_CH0  
The HEALTHY pin is an open drain output. High when all  
enabled output supplies are within the programmed levels.  
HEALTHY will ignore any disabled supply.  
There is a  
programmable glitch filter on the under-voltage and over-voltage  
sensors so that short transients outside of the limits will be  
ignored by HEALTHY. This pin can also be programmed to act  
as a Reset Output (nRESET). In this case, it releases with a  
programmable delay after all outputs are valid. When used, this  
pin should be pulled high by an external pull-up resistor.  
HEALTHY  
(nRESET)  
2
3
OUT  
IN  
The COMP1_CH0 (Channel 0 primary Compensation) pin is the  
primary feedback input of the channel 0 step-down buck  
controller. The COMP1_CH0 pin is internally connected to a  
programmable resistor divider.  
COMP1_CH0  
The COMP2_CH0 (Channel 0 secondary Compensation) pin is  
the secondary feedback input of the channel 0 step-down buck  
controller.  
4
5
IN  
IN  
COMP2_CH0  
VM_CH0  
The VM_CH0 (Channel 0 Voltage Monitor) pin connects the  
channel 0 step-down controller output. Internally the VM_CH0 pin  
connects to a programmable resistor divider.  
SDA (Serial Data) is an open drain bi-directional pin used as the  
6
7
I/O  
IN  
SDA  
SCL  
I2C data line. SDA must be tied high through a pull-up resistor.  
SCL (Serial Clock) is an open drain input pin used as the I2C  
clock line. SCL must be tied high through a pull-up resistor.  
The LSDRV_CH1 (Channel 1 Low-side Driver) pin is the lower  
switching node of the channel 1 synchronous step-down buck  
controller. Attach to the gate of n-channel MOSFET.  
8
9
OUT  
LSDRV_CH1  
HVSUP1  
PWR  
Channel 1 High Voltage Supply for Channel 1 buck driver.  
The HSDRV_CH1 (Channel 1 High-side Driver) pin is the upper  
switching node of the channel 1 synchronous step-down buck  
controller. Attach to the gate of p-channel MOSFET. A delay  
exists between the assertion of HSDRV_CH1 and assertion of  
LSDRV_CH1 to prevent excessive current flow during switching.  
The HOST_RESET pin is an active high reset input. When this  
pin is asserted high, the nRESET output will immediately go low.  
When HOST_RESET is brought low, nRESET will go high after a  
programmed reset delay. When pin 2 is used as a HEALTHY  
output, this pin needs to be attached to GND or VBATT via a  
resistor.  
10  
11  
OUT  
IN  
HSDRV_CH1  
HOST_RESET  
The COMP1_CH1 (Channel 1 primary Compensation) pin is the  
primary compensation input of the channel 1 step-down buck  
controller. The COMP1_CH1 pin is internally connected to a  
programmable resistor divider.  
12  
13  
IN  
IN  
COMP1_CH1  
COMP2_CH1  
The COMP2_CH1 (Channel 1 secondary Compensation) pin is  
the secondary compensation input of the channel 1 step-down  
buck controller.  
Summit Microelectronics, Inc  
2111 2.4 6/24/2008  
5

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