Datasheet > SMB117

SMB117

更新时间： 2022-12-29 05:19:47

品牌	Logo	应用领域
SUMMIT		/
页数	文件大小	规格书
32页	713K
描述
High-power, Four-channel Programmable DC-DC System Power Managers

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数据手册

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SMB117 数据手册

SMB113A/B/SMB117/A

Preliminary Information

INTERNAL BLOCK DIAGRAM

COMP2_CH[0,1,2,3]

VM_CH[0,1,2,3]

HVSUP[0,1,2,3]

Channel 0,1,2,3

HSDRV[0,1,2,3]

Synchronous buck

PWM Converter

100k

–

DUTY

CYCLE

LIMIT

–

I²C/SMBUS

SDA

SCL

DEADTIME

MAX LIMIT

LOW LIMIT

CLAMP

OSC

Fixed 250/400/

800/1000kHz

COMP1_CH[0,1,2,3]

–

OVER VOLTAGE

DETECTION

GLITCH

FILTER

LSDRV[0,1,2,3]

PWREN0

VREF

LEVEL

SEQUENCING

AND

SHIFTER

DIGITAL TO

ANALOG

–

MONITORING

LOGIC

UNDER VOLTAGE

DETECTION

GLITCH

FILTER

CONVERTER

VREF

ENABLE

GND

VBATT

VREF

BANDGAP

VDDCAP

–

VDD_CAP

UV2

2.5V

REGULATOR

–

LEVEL

UV1

SHIFTER

VREF

Figure 3 –SMB113A/B and SMB117/A internal block diagram. Programmable functional blocks include: level

shifters, digital to analog converter and the VM_CH[0,1,2,3] voltage dividers.

Summit Microelectronics, Inc

2111 2.4 6/24/2008

1 2 345 6 7...32

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