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ꢎ ꢏꢐ ꢑꢒ ꢓꢔꢕ ꢉꢋ ꢐꢓ ꢔꢒ ꢍꢓ ꢕꢓ ꢒꢑꢏ ꢀꢓ ꢕ ꢔꢑꢏ ꢋꢖ ꢐ ꢅꢊ ꢀ ꢀꢐ ꢖ ꢀ
SGUS055 − SEPTEMBER 2004
D
D
D
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
L1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
− 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
16-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− 256M-Byte Total Addressable External
Memory Space
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
†
Qualification Pedigree
Low-Price/High-Performance Floating-Point
Digital Signal Processors (DSPs):
320C67x (SM320C6712, C6712C, C6712D)
− Eight 32-Bit Instructions/Cycle
− 100-, 167-MHz Clock Rates
D
D
− 10-, 6-ns Instruction Cycle Times
− 600, 1000 MFLOPS
D
Advanced Very Long Instruction Word
(VLIW) C67x DSP Core
− Eight Highly Independent Functional
Units:
D
Two Multichannel Buffered Serial Ports
(McBSPs)
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
D
D
Two 32-Bit General-Purpose Timers
D
D
Instruction Set Features
− Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
Flexible Phase-Locked-Loop (PLL) Clock
Generator [C6712]
D
D
D
D
Flexible Software-Configurable PLL-Based
Clock Generator Module [C6712C/C6712D]
A Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins [12C/12D]
‡
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
CMOS Technology
− 0.13-µm/6-Level Copper Metal Process
(C6712C/C6712D)
Device Configuration
− Boot Mode: 8- and 16-Bit ROM Boot
− Endianness: Little Endian (12/12C)
Little Endian, Big Endian (12D)
− 0.18-µm/5-Level Metal Process (C6712)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Other trademarks are the property of their respective owners.
†
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but
is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life,
and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
‡
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ꢛꢣ ꢚꢟ ꢦ ꢟ ꢧ ꢛꢥ ꢞꢟ ꢠ ꢡꢨ ꢒꢗ ꢟ ꢙ ꢡ ꢢ ꢡꢝꢙ ꢛꢣ ꢟꢢ ꢜ ꢗ ꢚꢟ ꢦꢘꢜ ꢟ ꢘꢙ ꢘꢠꢚ ꢘꢜꢢ ꢡꢟ ꢚ ꢛꢠ ꢡꢗ ꢟ ꢥꢢ ꢩꢟꢪ ꢙꢫ
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Copyright 2004, Texas Instruments Incorporated
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1
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