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SM320C6203S14 PDF预览

SM320C6203S14

更新时间： 2024-11-24 03:31:39
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
64页 925K
描述
FLOATING-POINT DIGITAL SIGNAL PROCESSOR

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中文翻译

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SM320C6203S14 数据手册

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SGUS030B – APRIL 2000 – REVISED MAY 2001  
D
Highest Performance Floating-Point Digital  
Signal Processor (DSP) SMJ320C6701  
– 7-, 6-ns Instruction Cycle Time  
– 140-, 167-MHz Clock Rate  
– Eight 32-Bit Instructions/Cycle  
– Up to 1 GFLOPS Performance  
– Pin-Compatible With ’C6201 Fixed-Point  
DSP  
D
1M-Bit On-Chip SRAM  
– 512K-Bit Internal Program/Cache  
(16K 32-Bit Instructions)  
– 512K-Bit Dual-Access Internal Data  
(64K Bytes)  
D
D
32-Bit External Memory Interface (EMIF)  
– Glueless Interface to Synchronous  
Memories: SDRAM and SBSRAM  
– Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
D
D
D
SMJ: QML Processing to MIL-PRF-38535  
SM: Standard Processing  
Four-Channel Bootloading  
Direct-Memory-Access (DMA) Controller  
With an Auxiliary Channel  
Operating Temperature Ranges  
– Extended (W) –55°C to 115°C  
– Extended (S) –40°C to 90°C  
D
D
16-Bit Host-Port Interface (HPI)  
– Access to Entire Memory Map  
D
VelociTI Advanced Very Long Instruction  
Word (VLIW) ’C67x CPU Core  
– Eight Highly Independent Functional  
Units:  
Two Multichannel Buffered Serial Ports  
(McBSPs)  
– Direct Interface to T1/E1, MVIP, SCSA  
Framers  
– Four ALUs (Floating- and Fixed-Point)  
– Two ALUs (Fixed-Point)  
– Two Multipliers (Floating- and  
Fixed-Point)  
– Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
– ST-Bus-Switching Compatible  
– Up to 256 Channels Each  
– AC97-Compatible  
– Serial-Peripheral-Interface (SPI)  
Compatible (Motorola )  
D
D
Two 32-Bit General-Purpose Timers  
D
Instruction Set Features  
– Hardware Support for IEEE  
Single-Precision Instructions  
– Hardware Support for IEEE  
Double-Precision Instructions  
– Byte-Addressable (8-, 16-, 32-Bit Data)  
– 32-Bit Address Range  
– 8-Bit Overflow Protection  
– Saturation  
Flexible Phase-Locked-Loop (PLL) Clock  
Generator  
†
D
D
D
D
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
429-Pin Ceramic Ball Grid Array (CBGA)  
Package (GLP Suffix)  
0.18-µm/5-Level Metal Process  
– CMOS Technology  
– Bit-Field Extract, Set, Clear  
– Bit-Counting  
– Normalization  
3.3-V I/Os, 1.9-V Internal  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
VelociTI is a trademark of Texas Instruments Incorporated.  
Motorola is a trademark of Motorola, Inc.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 2001, Texas Instruments Incorporated  
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...64

中文翻译

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