Datasheet > SM2604T-6

SM2604T-6

更新时间： 2024-02-18 08:58:16

品牌	Logo	应用领域
铁电 - RAMTRON		时钟动态存储器光电二极管
页数	文件大小	规格书
33页	305K
描述
Synchronous DRAM, 4MX16, 4.3ns, CMOS, PDSO54, TSOP-54

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技术参数
数据手册

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SM2604T-6 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	TSOP, TSOP54,.46,32
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.02	风险等级：	5.83
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	4.3 ns
其他特性：	AUTO/SELF REFRESH	最大时钟频率 (fCLK)：	166 MHz
I/O 类型：	COMMON	交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PDSO-G54	JESD-609代码：	e0
内存密度：	67108864 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	16	功能数量：	1
端口数量：	1	端子数量：	54
字数：	4194304 words	字数代码：	4000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	4MX16
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP	封装等效代码：	TSOP54,.46,32
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	刷新周期：	4096
自我刷新：	YES	连续突发长度：	1,2,4,8,FP
子类别：	Other Memory ICs	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

SM2604T-6 数据手册

64Mbit – Enhanced SDRAM

8Mx8, 4Mx16 ESDRAM

Preliminary Datasheet

General Description

The 64Mbit ESDRAM is a high-speed SDRAM configured as four banks of DRAM with an SRAM row cache per bank

and a synchronous interface. All inputs are registered and all outputs are driven on the rising edge of clock. Within each

bank, the devices are organized as 4096 rows of 4096 bits each. Within each row, the 8Mx8 device has 512 column

address locations and the 4Mx16 device has 256 column locations.

Read and write accesses are accomplished by opening a row and selecting a column address location for the transaction.

The Bank Activate command instructs the device to open a row in one of the four banks, though all four banks may be

active simultaneously. A subsequent Read or Write command instructs the device to read data from or write data to a

specified column address location.

The device can be programmed to burst data in or out. Burst accesses start with the given column address location and

continue until the burst length is satisfied. Throughout the burst, the device internally generates column addresses

according to the burst type and burst length programmed into the Mode register.

An early auto-precharge feature allows the device to self-time its row precharge one clock cycle after a Read command is

issued, and one clock cycle following the last data word in a write burst. A precharge operation must occur before another

row is opened within the same bank.

Row Cache Operation

The ESDRAM architecture combines four banks of fast 22.5 ns DRAM with a 10.5 ns SRAM row cache per bank to

improve memory latency. Sustained high-speed bandwidth is achieved by pipelining operations internally. On a random

read access, a DRAM bank is activated and data is latched into the sense amplifiers in 12 ns. The sense amplifiers now

hold a row of data and the row is considered open. A Read command now causes the entire row to latch into the SRAM

row cache, and the data at the specified column address location is driven out in 10.5 ns.

Since the row data is latched into the SRAM row cache, the DRAM sense amplifiers are decoupled from the data. So the

DRAM precharge time can be hidden behind a burst read from the row cache. This minimizes subsequent page miss

latency. Since both precharge and RAS to CAS delays are hidden, the device supports an industry leading CAS latency of

one at clock frequencies up to 83 MHz, and CAS latency of two up to 166 MHz.

At 166 MHz, all but one cycle of the next random access to any location in the same bank can be hidden. This

dramatically increases sustained bandwidth by up to two times over standard SDRAM. For interleaved burst read

accesses, the entire precharge time is hidden and output data can be driven without any wait states.

No Write Transfer Mode

The ESDRAM architecture offers the system designer two different cache loading policies during write cycles. The cache

loading policy is programmed via the Mode Register Set command.

In Write Transfer (normal) mode the SRAM row cache is always loaded with the write data. This ensures coherency

between the row cache and the DRAM array, and allows read-modify-write cycles and simplified memory control logic.

In No Write Transfer mode, the row cache is not loaded during writes to the DRAM array. This allows continued access

to the previously cached read data without incurring a page miss penalty (closing the write row and re-opening the read

row). The ESDRAM can maintain four open read pages and four open write pages simultaneously in No Write Transfer

mode. This subject is also covered in the section on the Mode Register Set command.

Note: If a write hit occurs (the write page is already in the cache) the ESDRAM automatically updates the cache when the

data is written to the DRAM array, regardless of the Write Transfer mode setting. This maintains coherency.

This is a product in sampling or pre-production phase of development. Charac-

teristic data and other specifications are subject to change without notice.

Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921

PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com

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与SM2604T-6相关器件

型号	品牌	获取价格	描述	数据表
SM2604T-7.5	RAMTRON	获取价格	Synchronous DRAM, 4MX16, 4.5ns, CMOS, PDSO54, TSOP-54
SM2605Q-10	RAMTRON	获取价格	Synchronous DRAM, 2MX32, 4.7ns, CMOS, PQFP100, LQFP-100
SM2605Q-6	RAMTRON	获取价格	Synchronous DRAM, 2MX32, 4.3ns, CMOS, PQFP100, LQFP-100
SM2605Q-7.5	RAMTRON	获取价格	Synchronous DRAM, 2MX32, 4.5ns, CMOS, PQFP100, LQFP-100
SM260A	LRC	获取价格	Schottky Barrier Rectifiers Reverse Voltage 20 to100V
SM260A	TAYCHIPST	获取价格	SURFACE MOUNT SCHOTTKY BARRIER RECTIFIERS
SM260A	UNIOHM	获取价格	2.0 AMP SURFACE MOUNT SCHOTTKY BARRIER RECTIFIERS
SM260A	SECOS	获取价格	2.0 AMP Surface Mount Schottky Barrier Rectifiers
SM260A-E	LRC	获取价格	Schottky Barrier Rectifiers Reverse Voltage 20 to100V Forward Current 2.0A
SM260AF	SECOS	获取价格	20V ~200V 2.0 Amp Surface Mount Schottky Barrier Rectifiers

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