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SLG55031

更新时间： 2023-12-20 18:46:10

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SLG55031 数据手册

SLG55031

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Timing Diagram - Initial P-ON

V_CCto the SLG55031 must reach V_CCmin (4.75 V) before the device will begin to be operational. ENABLE¹must be asserted

100 s after 100% of V_CChas been attained. If V_DRAIN is present at a minimum of 3s prior to assertion of the ENABLE, the

Source will begin to ramp towards V_DRAIN after T_VT (10 s typically), the time required for the gate of the FET to be past turn

on threshold (typically 2.0 V). Carefully examine specific FET turn-on threshold as well as FET C-IN and if the values fall outside

of the range of values covered in the electrical specifications section of this document, consult Renesas for applications assis-

tance in determining the value of T_VT.

T_DRAIN_to_ENABLE

T_VCC_to_EN

VCC

ENABLE

High True Example

V_DRAIN

V_GATE

V_SOURCE

DONE

T_VT

T_slew

Diagram 1 Enable after VCC

000-0055031-102

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