Datasheet > SLG55031

SLG55031

更新时间： 2023-12-20 18:46:10

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SLG55031 数据手册

SLG55031

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If V_DRAIN is not present prior to the assertion ENABLE, the driven FET will be turned on immediately following assertion of

ENABLE and subsequent application of a voltage on the Drain of the FET will be directly applied to the Source (Diagram 2).

Again, V_CCmust have reached V_CC-MINbefore ENABLE will operate the device. V_Gate will be pulled to V_CCafter which the

V_Source will track the voltage applied to the Drain of the FET.

EN_to_DRAIN

T_VCC_to_EN

VCC

ENABLE

High True Example

V_DRAIN

V_GATE

V_SOURCE

DONE*

T_slew = Drain Slew

Diagram 2

1 T_V_CCto ENABLE = 100 s assertion delay (when V_CCinitially ramping up to 100% of V_CC).

2 Enable assertion transition time must be less than 1 s.

* If V_Drain = 0 V prior to assertion of ENABLE, DONE becomes true co-incident with assertion of ENABLE.

* In the case of V_DRAIN after ENABLE, the definition of Arrival and Ramp Time are not valid

000-0055031-102

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