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SL1935D/KG/NP4Q

更新时间： 2024-01-27 02:31:36
品牌 Logo 应用领域
英特尔 - INTEL 光电二极管商用集成电路
页数 文件大小 规格书
23页 620K
描述
Consumer Circuit, PDSO36, 7.50 MM, LEAD FREE, SSOP-36

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SL1935D/KG/NP4Q 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：SSOP
包装说明：SSOP,针数：36
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.25商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：R-PDSO-G36JESD-609代码：e3
长度：15.37 mm功能数量：1
端子数量：36最高工作温度：80 °C
最低工作温度：-20 °C封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH认证状态：Not Qualified
座面最大高度：2.64 mm最大压摆率：70 mA
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
表面贴装：YES温度等级：COMMERCIAL EXTENDED
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

SL1935D/KG/NP4Q 数据手册

 浏览型号SL1935D/KG/NP4Q的Datasheet PDF文件第2页浏览型号SL1935D/KG/NP4Q的Datasheet PDF文件第3页浏览型号SL1935D/KG/NP4Q的Datasheet PDF文件第4页浏览型号SL1935D/KG/NP4Q的Datasheet PDF文件第6页浏览型号SL1935D/KG/NP4Q的Datasheet PDF文件第7页浏览型号SL1935D/KG/NP4Q的Datasheet PDF文件第8页 
SL1935  
Bit1(POR)isthepower-on resetindicator, andthisisset  
The STOP condition can be generated after any data  
byte, if however it occurs during a byte transmission, the  
previous byte data is retained. To facilitate smooth fine  
tuning, the frequency data bytes are only accepted by  
the device after all 15 bits of frequency data have been  
received, or after the generation of a STOP condition.  
to a logic ‘1’ if the Vccd supply to the device has dropped  
o
below3V(at25 C),e.g. whenthedevice isinitiallyturned  
ON. The POR is reset to ‘0’ when the read sequence is  
terminatedby a STOP command. When POR is set high  
this indicates that the programmed information may  
have been corrupted and the device reset to the power  
up condition.  
Read mode  
Bit 2 (FL) indicates whether the synthesiser is phase  
locked, a logic ‘1’ is present if the device is locked, and  
a logic ‘0’ if the device is unlocked.  
When the device is in read mode, the status byte read  
from the device takes the form shown in Table 9b.  
Table 2. Programmable Features  
Programmable features  
Function  
Function as described above  
Function as described above.  
Function as described above.  
Synthesiser programmable divider  
Reference programmable divider  
Baseband filter path select  
Local oscillator select  
Function as described above.  
The charge pump current can be programmed by bits C1 & C0 (Table 5).  
The test modes are defined by bits T2 - T0 as described in Table 4.  
The general purpose port can be programmed by bit P0;  
Logic ‘1’ = on  
Charge pump current  
Test mode  
General purpose port, P0  
Logic ‘0’ = off (high impedance)  
The buffered crystal reference frequency can be switched to the BUFREF  
output by bit RE as described in Table 7. The BUFREF output defaults to  
the ‘ON’ condition at device power up.  
Buffered crystal reference output,  
BUFREF  
o
The typical key performance data at Vcc = 5V and +25 C ambient are detailed in Table 1.  
Table 3. Reference division ratios  
R2  
R1  
R0  
Ratio  
R4  
R3  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
4
8
16  
32  
64  
128  
256  
Illegal state  
5
10  
20  
40  
80  
160  
320  
Illegal state  
6
12  
24  
48  
96  
192  
384  
Illegal state  
7
14  
28  
56  
112  
224  
448  
5
12345678...23

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