Datasheet > SL1935D/KG/NP4Q

SL1935D/KG/NP4Q

更新时间： 2024-02-27 17:44:26

品牌	Logo	应用领域
英特尔 - INTEL		光电二极管商用集成电路
页数	文件大小	规格书
23页	620K
描述
Consumer Circuit, PDSO36, 7.50 MM, LEAD FREE, SSOP-36

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SL1935D/KG/NP4Q 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	36
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.25	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PDSO-G36	JESD-609代码：	e3
长度：	15.37 mm	功能数量：	1
端子数量：	36	最高工作温度：	80 °C
最低工作温度：	-20 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	认证状态：	Not Qualified
座面最大高度：	2.64 mm	最大压摆率：	70 mA
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
表面贴装：	YES	温度等级：	COMMERCIAL EXTENDED
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	DUAL
宽度：	7.5 mm	Base Number Matches：	1

SL1935D/KG/NP4Q 数据手册

SL1935

Table 1. QuickReferenceData

Characteristic

Value

Units

MHz

dBm

950 to 2150

-75 to -15

Operating range

Input dynamic range

VSWR with input match

Input NF

dBm

deg

+20

-5

2.0

0.2

0.7

@ -70dBm operating sensitivity

@ -60dBm operating sensitivity

IPIP3 @ -20dBm operating sensitivity

IPIP2@ -20dBm operating sensitivity

IPP1dB@ -20dBm operating sensitivity

Baseband output limit voltage

Gain match up to 22MHz

Phase match up to 22MHz

Gain flatness up to 30MHz

Local oscillator phase noise

SSB at 10kHz offset

In band LO reradiation from RF input

LO second harmonic interference level at input level of

-20dBm per carrier

dBc/Hz

dBm

dBc

-80

<-70

-55

dBc

-35

LNA second harmonic interference level at input level

of -25dBm per carrier

MHz

dBc/Hz

-152

PLL maximum comparison frequency

PLL phase noise at phase detector

Note: `6dB interstage filter loss assumed in external base band paths.

dBm assumes 75Ω characteristic impedance.

Quadrature Downconverter Section

FunctionalDescription

In normal application the tuner IF frequency of typically

950 to 2150MHz is fed direct to the SL1935 RF input

through an appropriate impedance match (Fig.16) and

LNB switching. The input stage is optimised for both NF

and signal handling.

General

The SL1935 is a complete wideband direct conversion

tuner incorporating an on board frequency synthesiser

andLNA/AGC, optimisedforapplicationindigitalsatellite

receiver systems. The device offers a highly integrated

The signal handling of the front end is designed to offer

immunity to input composite overload without the

requirement of a tracking filter. RF input impedance is

shown in Fig.3.

solutiontoasatellitetunerfunction, incorporatinganI C

businterfacecontroller, alowphasenoisePLLfrequency

synthesiser and all tuner analogue functionality. The

analogue blocks include the reference oscillator,

consistingoftwoindependentoscillators,aphasesplitter,

RF preamplifier with AGC facility, channel mixers and

baseband amplifiers incorporating two selectable

baseband paths, allowing for two externally definable

bandwidths. In this application two varactor tuned tanks,

a reference crystal and baseband filtering components

are required to complete the tuner system.

The RF input amplifier feeds an AGC stage and provides

system gain control. The system AGC gain range will

guarantee anoperating dynamicrange of-70to-20dBm.

TheAGCiscontrolledbytheAGCsenderandisoptimised

for S/N and S/I performance across the full dynamic

range. Details of the AGC characteristics, variations in

IIP3, IIP2, P1dB and NF are illustrated in Figs.4, 5, 6, 7,

and 8 respectively.

A buffered crystal frequency output is available to clock

the QPSK demodulator and powers up in the active

state.

The required I and Q local oscillator frequencies for

quadrature downconversion are generated by the on-

board reference oscillators designated ‘VCOS’ and

‘VCOV’. VCOSoperatesnominallyfrom1900to3000MHz

and is then divided by two to provide 950 to 1500MHz.

VCOV operates nominally from 1400 to 2200MHz. Only

TheI C businterfacecontrolsthefrequencysynthesiser,

the local oscillator, the baseband path selection, the

buffered reference frequency output and an external

switching port.

the oscillator selected via bit VS in the I C data

transmission is powered.

Figure 2 shows the device block diagram and pin

allocations are shown in Figure 1.

1 234 5 6 7...23

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