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SIT1552

更新时间： 2024-11-25 01:22:59
品牌 Logo 应用领域
SITIME /
页数 文件大小 规格书
11页 727K
描述
Smallest (1.2mm2), Smallest (1.2mm2), Ultra-Low Power, 32.768 kHz

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SIT1552 数据手册

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SiT1552  
Smallest (1.2mm2), Smallest (1.2mm2), Ultra-Low Power, 32.768 kHz  
Features  
Applications  
32.768 kHz ±5, ±10, ±20 ppm frequency stability options  
over temp  
World’s smallest TCXO in a 1.5 x 0.8 mm CSP  
Operating temperature ranges:  
. 0°C to +70°C  
Smart Meters (AMR)  
Health and Wellness Monitors  
Pulse-per-Second (pps) Timekeeping  
RTC Reference Clock  
. -40°C to +85°C  
Ultra-low power: <1 µA  
Vdd supply range: 1.5V to 3.63V  
Improved stability reduces system power with fewer  
network timekeeping updates  
Internal filtering eliminates external Vdd bypass cap and  
saves space  
Pb-free, RoHS and REACH compliant  
Electrical Specifications  
Table 1. Electrical Characteristics  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
Unit  
Condition  
Frequency andStability  
Output Frequency  
Fout  
32.768  
kHz  
-5.0  
5.0  
10  
Stability part number code =E  
Frequency StabilityOver  
Temperature[1]  
F_stab  
ppm  
-10  
-20  
Stability part number code =F  
Stability part number code =1  
Stability part number code =E  
Stability part number code =F  
Stability part number code =1  
1.8V ±10%  
(without Initial Offset [2]  
)
20  
-10  
10  
Frequency StabilityOver  
Temperature  
F_stab  
-13  
13  
ppm  
(with Initial Offset[2]  
)
-22  
22  
ppm  
ppm  
ppm  
-0.75  
-1.5  
-1.0  
0.75  
1.5  
1.0  
F_vdd  
Frequency Stability vs Voltage  
First Year Frequency Aging  
1.5V – 3.63V  
TA = 25°C, Vdd = 3.3V  
F_aging  
Jitter Performance (TA = over temp)  
µspp  
Long Term Jitter  
Period Jitter  
2.5  
81920 cycles (2.5 sec), 100samples  
nsRMS  
Cycles = 10,000, TA = 25°C, Vdd = 1.5V – 3.63V  
35  
Supply Voltage and Current Consumption  
Vdd  
Idd  
TA = -40°C to +85°C  
Operating Supply Voltage  
Core Supply Current [3]  
1.5  
3.63  
V
TA = 25°C, Vdd = 1.8V, LVCMOS Output configuration, No Load  
TA = -40°C to +85°C, Vdd = 1.5V – 3.63V, No Load  
0.99  
180  
μA  
1.52  
100  
t_Vdd_  
Ramp  
Vdd Ramp-Up 0 to 90% Vdd, TA = -40°C to +85°C  
Power-Supply Ramp  
Start-up Time atPower-up  
Notes:  
ms  
ms  
TA = -40°C +60°C, valid output  
TA = +60°C to +70°C, valid output  
TA = +70°C to +85°C, valid output  
300  
350  
380  
t_start  
1. No board level underfill. Measured as peak-to-peak/2. Inclusive of 3x-reflow and ±20% load variation. Tested with Agilent 53132A frequency counter. Due to  
the low operating frequency, the gate time must be ≥100 ms to ensure an accurate frequency measurement.  
2. Initial offset is defined as the frequency deviation from the ideal 32.768 kHz at room temperature, post reflow.  
3. Core operating current does not include output driver operating current or load current. To derive total operating current (no load), add core operating current  
+ output driver operating current, which is a function of the output voltage swing. See the description titled Calculating Load Current.  
Rev 1.31  
January 18, 2018  
www.sitime.com  
1234567...11

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