SI4706-D50

更新时间： 2024-01-13 23:46:55

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
36页	1353K
描述
HIGH-PERFORMANCE FM AND RDS/RBDS RECEIVER

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技术参数
数据手册

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SI4706-D50 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	2.17
商用集成电路类型：	AUDIO DEMODULATOR	Base Number Matches：	1

SI4706-D50 数据手册

Si4706-D50

Table 5. 2-Wire Control Interface Characteristics^1,2,3

(V_A= 2.7 to 5.5 V, V_D= 1.62 to 3.6 V, T_A= –20 to 85 °C)

Parameter

Symbol Test Condition

Min

Typ

—

Max

400

—

Unit

kHz

µs

SCLK Frequency

SCLK Low Time

SCLK High Time

SCL

1.3

0.6

—

LOW

—

µs

HIGH

SCLK Input to SDIO  Setup

—

µs

SU:STA

(START)

SCLK Input to SDIO  Hold

0.6

—

µs

HD:STA

(START)

SDIO Input to SCLK  Setup

100

—

900

—

µs

SU:DAT

4, 5

SDIO Input to SCLK  Hold

HD:DAT

SU:STO

SCLK Input to SDIO  Setup

0.6

(STOP)

STOP to START Time

SDIO Output Fall Time

1.3

—

µs

BUF

250

f:OUT

C_b

----------

1pF

20 + 0.1

SDIO Input, SCLK Rise/Fall Time

—

300

f:IN

r:IN

C_b

----------

1pF

20 + 0.1

SCLK, SDIO Capacitive Loading

Input Filter Pulse Suppression

Notes:

—

1. When V_D= 0 V, SCLK and SDIO are low impedance.

2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high

until after the first start condition.

4. The Si4706 delays SDIO by a minimum of 300 ns from the V_IHthreshold of SCLK to comply with the minimum t_HD:DAT

specification.

5. The maximum t_HD:DAThas only to be met when f_SCL= 400 kHz. At frequencies below 400 kHz, t_HD:DATmay be violated

as long as all other timing parameters are met.

Rev. 1.0

1...4 5 678 9 10...36

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