SI4706-D50

更新时间： 2024-01-23 22:04:18

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
36页	1353K
描述
HIGH-PERFORMANCE FM AND RDS/RBDS RECEIVER

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技术参数
数据手册

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SI4706-D50 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	2.17
商用集成电路类型：	AUDIO DEMODULATOR	Base Number Matches：	1

SI4706-D50 数据手册

Si4706-D50

Table 4. Reset Timing Characteristics^1,2,3

(V_A= 2.7 to 5.5 V, V_D= 1.62 to 3.6 V, T_A= –20 to 85 °C)

Parameter

Symbol

Min

100

Typ

—

Max

—

Unit

µs



RST Pulse Width and GPO1, GPO2/INT Setup to RST

GPO1, GPO2/INT Hold from RST

Important Notes:

SRST

—

HRST

1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until

after the first start condition.

3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the

rising edge of RST.

4. If GPO1 and GPO2 are actively driven by the user, then minimum t_SRSTis only 30 ns. If GPO1 or GPO2 is high

impedance, then minimum t_SRSTis 100 µs to provide time for on-chip 1 M devices (active while RST is low) to pull

GPO1 high and GPO2 low.

t_SRSTt_HRST

70%

RST

30%

70%

GPO1

30%

70%

GPO2

30%

Figure 1. Reset Timing Parameters for Busmode Select Method

Rev. 1.0

1...3 4 567 8 9...36

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