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SI4205-BMR PDF预览

SI4205-BMR

更新时间: 2024-11-15 19:59:19
品牌 Logo 应用领域
芯科 - SILICON 电信电信集成电路
页数 文件大小 规格书
38页 681K
描述
RF and Baseband Circuit, CMOS, 8 X 8 MM, LGA-32

SI4205-BMR 技术参数

生命周期:Obsolete零件包装代码:LGA
包装说明:LFLGA,针数:32
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:S-XBGA-B32
长度:8 mm功能数量:1
端子数量:32最高工作温度:85 °C
最低工作温度:-20 °C封装主体材料:UNSPECIFIED
封装代码:LFLGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.42 mm标称供电电压:2.85 V
表面贴装:YES技术:CMOS
电信集成电路类型:RF AND BASEBAND CIRCUIT温度等级:OTHER
端子形式:BUTT端子节距:0.8 mm
端子位置:BOTTOM宽度:8 mm
Base Number Matches:1

SI4205-BMR 数据手册

 浏览型号SI4205-BMR的Datasheet PDF文件第2页浏览型号SI4205-BMR的Datasheet PDF文件第3页浏览型号SI4205-BMR的Datasheet PDF文件第4页浏览型号SI4205-BMR的Datasheet PDF文件第5页浏览型号SI4205-BMR的Datasheet PDF文件第6页浏览型号SI4205-BMR的Datasheet PDF文件第7页 
Aero I  
AEROI TRANSCEIVER  
FOR GSM AND GPRS WIRELESS COMMUNICATIONS  
Features  
Pin Assignments  
(Top View)  
„
„
„
Single 8 x 8 mm package  
CMOS process technology  
„
Quad-band support:  
z GSM 850 Class 4, small MS  
z E-GSM 900 Class 4, small MS  
z DCS 1800 Class 1  
Si4205-BM  
(For pin description see page 33)  
Integrated GSM/GPRS  
transceiver including:  
z PCS 1900 Class 1  
z Low-IF receiver  
28  
27  
26  
25  
24  
23  
22  
32  
31  
„
„
„
GPRS Class 12 compliant  
z Universal baseband interface  
z Offset-PLL transmitter  
z Dual RF synthesizer  
Integrated VCOs, frequency  
synthesizers, and tuning inductors  
21  
20  
19  
18  
17  
16  
15  
1
2
3
4
5
6
7
RFIGN  
RFIGP  
RFIDN  
RFIDP  
RFIPN  
RFIPP  
GND  
3-wire serial interface  
RXQN  
RXIP  
RXIN  
TXIP  
GND  
2.7 V to 3.0 V operation  
GND  
„
TXIN  
GND  
GND  
TXQP  
TXQN  
Applications  
29  
30  
8
9
10  
11  
12  
13  
14  
„
„
Multi-band GSM/GPRS digital cellular handsets  
Multi-band GSM/GPRS wireless data modems  
Ordering Information:  
See page 34.  
Description  
The Aero I transceiver is a complete RF front end for multi-band GSM  
and GPRS wireless communications. The transmit section interfaces  
between the baseband processor and the power amplifier. The receive  
section interfaces between the RF band-select SAW filters and the  
baseband processor. All sensitive components, such as RF/IF VCOs,  
loop filters, and tuning inductors, are completely integrated into a single  
compact package.  
Patents pending  
Functional Block Diagram  
Si4205  
GSM  
LNA  
PGA  
PGA  
ADC  
ADC  
PGA  
PGA  
DAC  
I
DCS  
PCS  
LNA  
LNA  
DAC  
Q
XOUT  
0 / 90  
100 kHz  
I
DET  
GSM  
PA  
PA  
I
DCS  
PCS  
Q
VC-TCXO  
13 or 26 MHz  
RF  
PLL  
IF  
PLL  
XIN  
AFC  
Rev. 1.0 12/03  
Copyright © 2003 by Silicon Laboratories  
Aero I  

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