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SI3227-E-GQ PDF预览

SI3227-E-GQ

更新时间: 2024-01-12 15:06:48
品牌 Logo 应用领域
芯科 - SILICON 电信电信集成电路
页数 文件大小 规格书
46页 496K
描述
SLIC, CMOS, PQFP64, ROHS COMPLIANT, MS-026ACD, TQFP-64

SI3227-E-GQ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TFQFP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.8
JESD-30 代码:S-PQFP-G64长度:10 mm
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260座面最大高度:1.2 mm
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:SLIC
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:10 mm
Base Number Matches:1

SI3227-E-GQ 数据手册

 浏览型号SI3227-E-GQ的Datasheet PDF文件第2页浏览型号SI3227-E-GQ的Datasheet PDF文件第3页浏览型号SI3227-E-GQ的Datasheet PDF文件第4页浏览型号SI3227-E-GQ的Datasheet PDF文件第5页浏览型号SI3227-E-GQ的Datasheet PDF文件第6页浏览型号SI3227-E-GQ的Datasheet PDF文件第7页 
Si3226/27 +  
Si3208/09  
DUAL PROSLIC® WITH DC-DC CONTROLLER  
Features  
Performs all BORSCHT functions  
Ideal for short- or long-loop applicationsOn-hook transmission  
Internal balanced or unbalanced ringingLoop or ground start operation  
Low power consumption  
Low-power sleep mode  
Smooth polarity reversal  
DTMF generator/decoder  
A-Law/µ-Law companding,  
linear PCM  
Software-programmable parameters:  
Ringing frequency, amplitude,  
cadence, and waveshape  
Two-wire ac impedance  
PCM and SPI bus digital interfaces  
with programmable interrupts  
GCI/IOM-2 mode support  
3.3 V operation  
GR-909 loop diagnostics  
Audio diagnostics with loopback  
Pb-free/RoHS-compliant packaging  
Transhybrid balance  
DC current loop feed (10–45 mA)  
Loop closure and ring trip thresholds  
Ground key detect threshold  
Integrated dc-dc controller  
Wideband CODEC (Si3227)  
Applications  
Customer Premises Equipment (CPE)  
Optical Network Terminals (ONT)  
Private Branch Exchange (PBX)  
Cable EMTAs, ATAs, VoIP  
Gateways  
Ordering Information  
Description  
See page 38.  
The Si3226/27 Dual ProSLIC® chipsets each consist of a low-voltage CMOS  
device integrating both SLIC and CODEC functionality in combination with a high-  
voltage linefeed IC (LFIC). The chipset provides two complete foreign exchange  
station (FXS) telephony interfaces. The Si3226/27 operate from a single 3.3 V  
supply and interface to standard PCM/SPI or GCI bus digital interfaces. A built-in  
dc-dc controller automatically generates the optimal battery voltage required for  
each line-state, optimizing efficiency and minimizing heat generation. Self-testing  
and metallic loop testing (MLT), e.g., GR-909, is facilitated by the built-in DSP,  
monitor ADC, and test load. The companion Si3208/09 LFICs are available with  
voltage ratings up to –135 V to support high power ringing and the Si3227  
supports wideband audio for better-than-PSTN voice quality (see Ordering Guide  
below). The Si3226/27 are available in a 64-pin thin quad flat package (TQFP);  
the LFICs are available in a 40-pin quad, flat, no-lead package (QFN).  
Patents pending  
Functional Block Diagram  
Si3226/27  
Si3208/09  
CODEC SLIC  
PCM/  
GCI  
Interface  
FSYNC  
DRX  
DTMF &  
Tone Gen  
Linefeed  
TIP  
ADC  
Control  
DTX  
Channel 1  
RING  
Caller ID  
Linefeed  
Monitor  
CS  
SDI  
DAC  
SPI  
Control  
Interface  
Ringing  
Generator  
SDO  
SCLK  
INT  
SLIC  
Linefeed  
Control  
CODEC  
DSP  
TIP  
Line Diagnostics  
ADC  
RST  
Channel 2  
RING  
Linefeed  
Monitor  
DAC  
PCLK  
DC-DC Controllers  
PLL  
VBAT  
DC-DC BOM  
VDC  
Rev. 1.2 10/10  
Copyright © 2010 by Silicon Laboratories  
Si3226/27 + Si3208/09  
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).  

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