Data Sheet
Rev.1.0
12.04.2013
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
Voltage on any pin relative to VSS
SYMBOL
VDD
VDDQ
VDDL
VIN, VOUT
MIN
-0.4
-0.4
-0.4
-0.4
MAX
UNITS
1.975
1.975
1.975
1.975
V
V
V
V
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
II
µA
Command/Address
RAS#, CAS#, WE#, S#, CKE
-16
16
CK, CK#
DM
-16
-2
16
2
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-5
5
µA
µA
)
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
IVREF
-8
8
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
SYMBOL
VDD
MIN
1.425
1.425
NOM
1.5
1.5
MAX
1.575
1.575
UNITS
V
V
V
V
V
V
V
VDDQ
VDDL
VREF
VTT
VIH (DC)
VIL (DC)
VDDL Supply Voltage
1.425
1.5
0.50 x VDDQ
0.50 x VDDQ
1.575
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
0.49 x VDDQ
0.49 x VDDQ-20mV
VREF + 0.1
-0.3
0.51x VDDQ
0.51x VDDQ+20mV
VDDQ + 0.3
VREF – 0.1
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VIH (AC)
VIL (AC)
MIN
VREF + 0.175
-
MAX
-
VREF - 0.175
UNITS
V
V
CAPACITANCE
At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
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