Datasheet > SG-210SDD80.000MHZL0

SG-210SDD80.000MHZL0

更新时间： 2024-01-18 21:14:28

品牌	Logo	应用领域
精工 - SEIKO		/
页数	文件大小	规格书
1页	169K
描述
Oscillator,

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技术参数
数据手册

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SG-210SDD80.000MHZL0 技术参数

是否Rohs认证：	符合	生命周期：	End Of Life
Reach Compliance Code：	compliant	风险等级：	5.57
JESD-609代码：	e4	端子面层：	Gold (Au)
Base Number Matches：	1

SG-210SDD80.000MHZL0 数据手册

Crystal oscillator

Epson Toyocom

Product Number (please contact us)

X1G0029x1xxxx00

CRYSTAL OSCILLATOR

Low Profile / LOW-JITTER SPXO

SG-210S*D

Frequency range

Supply voltage

50.000 MHz to 80.000 MHz

1.8 V / 2.5 V / 3.3 V

Current consumption : 7.0 mA Max.

(SDD: 2.5 V No load condition 80 MHz)

Function

External dimensions

Standby(

)

Actual size

2.5 × 2.0 × 0.8 mm

Specifications (characteristics)

Specifications

Item

Symbol

Conditions / Remarks

Store as bare product.

SG-210SED

SG-210SDD

50.000 MHz to 80.000 MHz

2.5 V Typ.

SG-210SCD

Output frequency range

Supply voltage

1.8 V Typ.

1.6 V to 2.2 V

3.3 V Typ.

2.7 V to 3.6 V

VCC

2.2 V to 3.0 V

Storage temperature

Operating temperature

T_stg

T_use

-40 C to +125 °C

-40 C to +85 °C

B: 50 × 10^-6, C: 100 × 10^-6

L: 50 × 10^-6, M: 100 × 10^-6

7.0 mA Max.

-20 C to +70 C

-40 C to +85 C

No load condition

Frequency tolerance

f_tol

Current consumption

ICC

6.0 mA Max.

8.0 mA Max.

Stand-by current

Symmetry

I_std

SYM

VOH

VOL

ST =GND

10.0 µA Max.

45 % to 55 %

VCC -0.4 V Min.

0.4 V Max.

50 % VCC level,L_CMOS  30 pF

IOH=-8 mA(SCD,SDD), -4 mA(SED)

IOL= 8 mA(SCD,SDD), 4 mA(SED)

Output voltage

Output load condition

(CMOS)

L_CMOS

30 pF Max.

VIH

VIL

70 % VCC Min.

30 % VCC Max.

Input voltage

ST terminal

20 % VCC to 80 % VCC level,

L_CMOS  30 pF

t=0 at 90 % VCC

Deterministic Jitter

Random Jitter

Rise time / Fall time

Start-up time

tr/ tf

4 ns Max.

2 ms Max.

t_str

tDJ

tRJ

0.1 ps Typ.

3.2 ps Typ.

30 ps Typ.

0.1 ps Typ.

2.7 ps Typ.

25 ps Typ.

Jitter *1

L_CMOS  15 pF

tRMS

Peak to Peak

Offset frequency:

12 kHz to 20 MHz

+25 °C, First year,

VCC= 1.8 V, 2.5 V, 3.3 V

+25 °C, 10 years,

Phase Jitter

tPJ

1.0 ps Max.

3 × 10^-6/ year Max..

Frequency aging

f_aging

10 × 10^-6/ 10 years Max.

VCC= 1.8 V, 2.5 V, 3.3 V

*1 Based on DTS-2075 Digital timing system made from WAVECREST with jitter analysis software VISI6.

External dimensions

(Unit:mm)

Footprint (Recommended)

(Unit:mm)

2.50.15

(ex. 0.01 µF)

Resist

50.00B

B631A

1.1

0.9

0.8

Pin map

Connection

GND

OUT

1.7

VCC

Note.

ST pin = HIGH or "open" : Specified frequency output.

ST pin = LOW : Output is high impedance, oscillation stops.

To maintain stable operation, provide a 0.01uF to

0.1uF by-pass capacitor at a location as near as

possible to the power source terminal of the crystal

product (between Vcc - GND).

http://www.epsontoyocom.co.jp

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