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SDTC124EET1 PDF预览

SDTC124EET1

更新时间: 2024-11-26 11:58:47
品牌 Logo 应用领域
安森美 - ONSEMI 晶体晶体管
页数 文件大小 规格书
13页 145K
描述
Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

SDTC124EET1 数据手册

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DTC114EET1 Series,  
SDTC114EET1 Series  
Bias Resistor Transistor  
NPN Silicon Surface Mount Transistor  
with Monolithic Bias Resistor Network  
This new series of digital transistors is designed to replace a single  
device and its external resistor bias network. The BRT (Bias Resistor  
Transistor) contains a single transistor with a monolithic bias network  
consisting of two resistors; a series base resistor and a baseemitter  
resistor. The BRT eliminates these individual components by  
integrating them into a single device. The use of a BRT can reduce  
both system cost and board space. The device is housed in the  
SC75/SOT416 package which is designed for low power surface  
mount applications.  
http://onsemi.com  
NPN SILICON  
BIAS RESISTOR TRANSISTORS  
PIN 3  
COLLECTOR  
(OUTPUT)  
Features  
PIN 1  
R1  
Simplifies Circuit Design  
Reduces Board Space  
Reduces Component Count  
The SC75/SOT416 Package Can be Soldered Using Wave or  
Reflow  
BASE  
(INPUT)  
R2  
PIN 2  
EMITTER  
(GROUND)  
The Modified GullWinged Leads Absorb Thermal Stress During  
Soldering Eliminating the Possibility of Damage to the Die  
PbFree Packages are Available  
3
S Prefix for Automotive and Other Applications Requiring Unique  
Site and Control Change Requirements; AECQ101 Qualified and  
PPAP Capable  
2
1
SC75 (SOT416)  
CASE 463  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
A
STYLE 1  
Rating  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
Symbol  
Value  
50  
Unit  
Vdc  
V
CBO  
CEO  
MARKING DIAGRAM  
V
50  
Vdc  
I
C
100  
mAdc  
THERMAL CHARACTERISTICS  
xx M G  
G
Rating  
Symbol  
Value  
Unit  
Total Device Dissipation,  
P
D
FR4 Board (Note 1) @ T = 25°C  
Derate above 25°C  
200  
1.6  
mW  
mW/°C  
A
xx  
=
Specific Device Code  
xx = (Refer to page 2)  
Date Code*  
Thermal Resistance,  
R
q
JA  
600  
°C/W  
M
G
=
=
JunctiontoAmbient (Note 1)  
PbFree Package  
Total Device Dissipation,  
P
D
(Note: Microdot may be in either location)  
FR4 Board (Note 2) @ T = 25°C  
Derate above 25°C  
300  
2.4  
mW  
mW/°C  
A
*Date Code orientation may vary depending  
upon manufacturing location.  
Thermal Resistance,  
R
q
JA  
400  
°C/W  
JunctiontoAmbient (Note 2)  
ORDERING INFORMATION  
See detailed ordering, marking, and shipping information in  
the package dimensions section on page 2 of this data sheet.  
Junction and Storage Temperature  
Range  
T , T  
55 to +150  
°C  
J
stg  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. FR4 @ Minimum Pad  
2. FR4 @ 1.0 × 1.0 Inch Pad  
©
Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
May, 2012 Rev. 12  
DTC114EET1/D  

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