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SDA5555FLPO PDF预览

SDA5555FLPO

更新时间: 2024-01-19 16:45:45
品牌 Logo 应用领域
东电化 - TDK 光电二极管商用集成电路
页数 文件大小 规格书
176页 2016K
描述
Consumer Circuit, PDIP52, 0.600 INCH, PLASTIC, MS-020, SDIP-52

SDA5555FLPO 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:SDIP,针数:52
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.66其他特性:ALSO OPERATES WITH 3V TO 3.6V SUPPLY
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:R-PDIP-T52
长度:45.95 mm功能数量:1
端子数量:52最高工作温度:70 °C
最低工作温度:-10 °C封装主体材料:PLASTIC/EPOXY
封装代码:SDIP封装形状:RECTANGULAR
封装形式:IN-LINE, SHRINK PITCH认证状态:Not Qualified
座面最大高度:4.83 mm最大供电电压 (Vsup):2.75 V
最小供电电压 (Vsup):2.25 V表面贴装:NO
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:1.778 mm端子位置:DUAL
宽度:15.24 mmBase Number Matches:1

SDA5555FLPO 数据手册

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SDA 55xx  
DATA SHEET  
Contents  
Page  
Section  
Title  
8
1.  
Introduction  
8
1.1.  
General Features  
8
1.1.1.  
1.1.2.  
1.1.3.  
1.1.4.  
1.1.5.  
1.1.6.  
1.2.  
External Crystal and Programmable Clock Speed  
8
Microcontroller Features  
9
Memory  
9
Display Features  
9
Acquisition Features  
9
Ports  
11  
Overview of Current Versions and Packages for SDA 55xx  
12  
12  
12  
12  
13  
13  
14  
14  
14  
15  
15  
15  
15  
15  
15  
16  
16  
16  
16  
16  
16  
16  
16  
16  
18  
18  
18  
19  
19  
20  
20  
20  
20  
20  
20  
20  
21  
2.  
Functional Description  
Clock System  
2.1.  
2.1.1.  
General Function  
System Clock  
2.1.2.  
2.1.3.  
Pixel Clock  
2.1.4.  
Related Registers  
Slicer and Data Acquisition  
General Function  
Slicer Architecture  
Distortion Processing  
Noise  
2.2.  
2.2.1.  
2.2.2.  
2.2.2.1.  
2.2.2.1.1.  
2.2.2.1.2.  
2.2.2.1.3.  
2.2.2.2.  
2.2.3.  
Frequency Attenuation  
Group Delay  
Data Separation  
H/V-Synchronization  
Acquisition Interface  
Framing Code Check  
Framing Code FC1  
Framing Code FCVPS  
Framing Code FC3  
Framing Code FCWSS  
FC Check Select  
2.2.4.  
2.2.4.1.  
2.2.4.1.1.  
2.2.4.1.2.  
2.2.4.1.3.  
2.2.4.1.4.  
2.2.4.1.5.  
2.2.4.2.  
2.2.4.3.  
2.2.5.  
Interrupts  
VBI Buffer and Memory Organization  
Related Registers  
RAM Registers  
2.2.5.1.  
2.2.5.1.1.  
2.2.5.1.2.  
2.2.6.  
Field Parameters  
Line Parameters  
Recommended Parameter Settings  
Microcontroller  
2.2.7.  
2.2.8.  
Architecture  
2.2.8.1.  
2.2.8.1.1.  
2.2.8.1.2.  
2.2.8.1.3.  
2.2.8.1.4.  
2.2.8.1.5.  
CPU Hardware  
Instruction Decoder  
Program Control Section  
Internal Data RAM  
Arithmetic/Logic Unit (ALU)  
Boolean Processor  
2
Sept. 10, 2004; 6251-556-3DS  
Micronas  

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