Datasheet > SAA8M16YX6XV4TL

SAA8M16YX6XV4TL

更新时间： 2024-11-13 21:53:39

品牌	Logo	应用领域
其他 - ETC		动态存储器双倍数据速率
页数	文件大小	规格书
13页	256K
描述
DOUBLE DATA RATE (DDR) SDRAM

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中文翻译

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数据手册

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SAA8M16YX6XV4TL 数据手册

128Mb: x4, x8, x16

DDR SDRAM

DOUBLE DATA RATE

(DDR) SDRAM

Timing – Cycle Time

7.5ns @ CL = 2.5 (PC2100)

10ns @ CL = 2.5 (PC1600)

-75A

-8A

Part number example:

SAA16M8T95AV4TL-75A

•

PC1600 and PC2100 compatible

(For part numbers prior to December

2004ꢀ refer to page 13 for decoding.)

VDD = +2.5V 0.2Vꢀ VDDꢁ = +2.5V 0.2V

Bi-directional data strobe (DꢁS) transmitted/ received with

dataꢀ i.e.ꢀ source-synchronous data capture (x16 has two –

one per byte)

•

Internalꢀ pipelined double-data-rate (DDR) architecture;

two data accesses per clock cycle

•

Differential clock inputs (CK and CK#)

Commands entered on each positive CK edge

DꢁS edge-aligned with data for READs; center-aligned

with data for WRITEs

•

DLL to align Dꢁ and DꢁS transitions with CK

Four internal banks for concurrent operation

Data mask (DM) for masking write data (x16 has two –

one per byte)

•

Programmable burst lengths: 2ꢀ 4ꢀ or 8

Auto precharge option

Auto Refresh

Longer lead TSOP for improved reliability (OCPL)

2.5V I/O (SSTL_2 compatible)

Options:

Designation:

Family

SpecTek Memory

SAA

Configuration

32 Meg x 4 (8 Meg x 4 x 4 banks)

16 Meg x 8 (4 Meg x 8 x 4 banks)

8 Meg x 16 (2 Meg x 16 x 4 banks)

32M4

16M8

8M16

Design ID

DDR 128 Megabit Design

(Call SpecTek Sales for details on

availability of “x” placeholders)

Yx6x

Voltage and refresh

2.5Vꢀ Auto Refresh

2.5Vꢀ Self or Auto Refresh

Plastic Package – OCPL

66-pin TSOP

(400 mil widthꢀ 0.65mm pin pitch)

PDF: 09005aef80505d1b / Source: 09005aef80469e44

128Mb: x4, x8, x16 DDR SDRAM

Rev: 11/23/2004

SpecTek reserves the right to change products or specifications

www.spectek.com

12 3 4 5 6 7...13

中文翻译

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