Datasheet > SAA5361HL/M1/1651

SAA5361HL/M1/1651

更新时间： 2022-05-16 23:30:24

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
28页	155K
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SAA5361HL/M1/1651 TSG0537/M1

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Philips Semiconductors

Product speciﬁcation

Multi page intelligent teletext decoder

SAA5360; SAA5361

12.3 Application notes

12.3.2 SYMBOL EXPLANATIONS

Ports AD0 to AD7 of the microcontroller can be connected

to pins D0 to D7 of the SRAM in any order.

Each timing symbol has five characters. The first character

is always ‘t’ (time). Depending on their positions, the other

characters indicate the name of a signal or the logical

status of that signal.

For the addressing, the lower group of address lines

(A0 to A8) and the upper group of address lines

(A9 to A14, A15_BK, RAMBK0 and RAMBK1) may be

connected in any order within the groups, provided that the

full 256 kbytes of external SRAM is used.

The designations are:

A = Address

C = Clock

Fig.5 shows the application diagram of the SAA5361 with

external SRAM connections.

D = Input data

When using an external SRAM smaller than 256 kbytes,

the relevant number of bits from the microcontroller

address bus should be disconnected, always removing the

most significant bits first.

H = Logic level HIGH

I = Instruction (program memory contents)

L = Logic level LOW, or ALE

P = PSEN

For power saving modes, it might be advisable to control

the CE pin of the SRAM module(s) using one of the

microcontroller ports to de-select the SRAM.

Q = Output data

R = RD signal

12.3.1 EXTERNAL DATA MEMORY ACCESS

t = Time

Table 4 External data memory access (see Fig.6 and

V = Valid

Fig.7)

W = WR signal

SYMBOL

t_RLRH

PARAMETER

RD pulse width

WR pulse width

TYPICAL⁽¹⁾UNIT

X = No longer a valid logic level

Z = Float

250

t_WLWH

t_RLDV

t_RHDX

t_RHDZ

RD LOW to valid data in 198

Examples:

t_AVLL= time for address valid to ALE LOW.

Data hold after RD

Data ﬂoat after RD

t_LLPL= time for ALE to PSEN LOW.

tbd

132

t_LLWL

ALE LOW to RD or

WR LOW

t_AVWL

Address valid to WR

LOW or RD LOW

172

t_QVWX

t_WHQX

t_RLAZ

Data valid to WR LOW 89

Data hold after WR

RD LOW to address

ﬂoat

tbd

t_WHLH

RD or WR HIGH to

ALE HIGH

Note

1. The timings are only valid for the nominal 12 MHz

clock provided to the microcontroller.

2005 Mar 09

1...19 20 212223 24 25...28

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