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SAA5361HL/M1/1651 PDF预览

SAA5361HL/M1/1651

更新时间: 2022-05-16 23:30:24
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
28页 155K
描述
SAA5361HL/M1/1651 TSG0537/M1

SAA5361HL/M1/1651 数据手册

 浏览型号SAA5361HL/M1/1651的Datasheet PDF文件第7页浏览型号SAA5361HL/M1/1651的Datasheet PDF文件第8页浏览型号SAA5361HL/M1/1651的Datasheet PDF文件第9页浏览型号SAA5361HL/M1/1651的Datasheet PDF文件第11页浏览型号SAA5361HL/M1/1651的Datasheet PDF文件第12页浏览型号SAA5361HL/M1/1651的Datasheet PDF文件第13页 
Philips Semiconductors  
Product specification  
Multi page intelligent teletext decoder  
SAA5360; SAA5361  
SYMBOL  
A15_BK  
PIN TYPE  
DESCRIPTION  
33  
34  
35  
O
address line 15  
SYNC_FILTER  
IREF  
I/O CVBS sync filter input; this pin should be connected to VSSA via a 100 nF capacitor  
I
reference current input for analog circuits and connected to VSSA via a 24 kΩ  
resistor  
A13  
A12  
A3  
36  
37  
38  
39  
40  
41  
O
O
O
O
O
O
address line 13  
address line 12  
address line 3  
address line 2  
address line 1  
A2  
A1  
FRAME  
de-interlace output synchronized with the VSYNC pulse to produce a  
non-interlaced display by adjustment of the vertical deflection circuits  
VPE  
42  
43  
I
OTP programming voltage input; connect to ground  
COR  
O
output which allows selective contrast reduction of the TV picture to enhance a  
mixed mode display; open-drain; active LOW  
n.c.  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
I/O not connected  
VDDA  
B
-
3.3 V analog supply voltage  
O
O
O
O
O
O
O
I
pixel rate output of the blue colour information  
G
pixel rate output of the green colour information  
R
pixel rate output of the red colour information  
A0  
address line 0  
RAMBK1  
RAMBK0  
VDS  
HSYNC  
RAMBK SFR selection bits input 1 for external program SRAM data storage  
RAMBK SFR selection bits input 0 for external program SRAM data storage  
video or data switch push-pull output for dot rate fast blanking  
Schmitt-triggered input for a TTL-level version of the horizontal sync pulse; the  
polarity of this pulse is programmable by register bit TXT1.H POLARITY  
n.c.  
54  
55  
I/O not connected  
VSYNC  
I
Schmitt-triggered input for a TTL-level version of the vertical sync pulse; the polarity  
of this pulse is programmable by register bit TXT1.V POLARITY  
n.c.  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
O
O
O
not connected  
not connected  
not connected  
n.c.  
n.c.  
n.c.  
I/O not connected  
VSSP  
n.c.  
-
I
periphery ground  
not connected (internal pull-up)  
core ground  
VSSC  
VDDC  
A11  
A10  
A9  
-
-
3.3 V core supply voltage  
address line 11  
O
O
O
O
O
-
address line 10  
address line 9  
A8  
address line 8  
n.c.  
not connected  
OSCGND  
crystal oscillator ground  
2005 Mar 09  
10  

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