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SA2400ABE

更新时间： 2024-01-16 23:09:43
品牌 Logo 应用领域
恩智浦 - NXP ISM频段信息通信管理
页数 文件大小 规格书
34页 290K
描述
Single chip transceiver for 2.45 GHz ISM band

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SA2400ABE 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP,针数：48
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.82JESD-30 代码：S-PQFP-G48
长度：7 mm功能数量：1
端子数量：48最高工作温度：85 °C
最低工作温度：-30 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH认证状态：Not Qualified
座面最大高度：1.6 mm标称供电电压：3.3 V
表面贴装：YES技术：BICMOS
电信集成电路类型：RF AND BASEBAND CIRCUIT温度等级：OTHER
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD宽度：7 mm
Base Number Matches：1

SA2400ABE 数据手册

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Philips Semiconductors  
Product data  
Single chip transceiver for 2.45 GHz ISM band  
SA2400A  
9. SA2400A RECEIVER  
The baseband output signal extends from DC to 8 MHz, and the out-of-band frequency begins from 11 MHz. The modulated test signal used is  
11 Msymbols/sec QPSK with raised cosine filtering (50% excess bandwidth for 11 Msymbols/sec). The LO frequency is the same as the  
Receiver channel center frequency, as the IF output is at 0 Hz.  
Table 6. SA2400A Receiver properties  
T
amb  
= 25 °C; V = 3.3 V; f = 2.45 GHz.  
CC LO  
Specification  
Conditions  
Min  
Typ  
Max  
Units  
RF input frequency range  
S11 (RF input)  
Typical  
2.4  
2.5  
GHz  
Incl balun+matching. 50 Ω unbalanced. Note 3.  
LNA in high gain (see reg. description 0x06)  
LNA in low gain  
–10  
–7  
–
–
dB  
dB  
Maximum Rx voltage gain  
Max RF input level  
RF input to I or Q outputs  
90  
93  
–
–
–
–
dB  
Including application, AGCTARGET = +5. Note 1.  
–10  
–20  
dBm  
dBm  
To maintain nominal IQ output levels as defined  
below (“nominal I and Q output voltage”)  
–
IQ Output DC error (relative to signal, –80 dBm < P  
< –20 dBm, 1 MHz sinewave  
–
–
–20  
dBc  
input  
5 µs after AGC set)  
output. Note 3.  
AGC settling time  
(indicated by AGC_SET digital  
output)  
Initiated by AGC_RESET input. Constant RF input  
within this settling time. Begins after TX to RX  
switching time. Measured from AGC_RESET 0–1  
transition. AGC delay registers (0x05) at default or  
smaller values. Note 2.  
a) First instance  
–
–
–
–
8
µs  
µs  
nd  
b) 2 or subsequent instances  
11  
AGC Max Gain settling time  
AGC forced to GMAX by:  
a) TX to RX mode transition.  
–
–
–
–
0
3
µs  
µs  
(measured after 5 µs TX–RX settling time).  
b) Pulse on AGC_RESET pin  
(measured from end of programming)  
Note 2.  
Note 2.  
AGC Max Gain adjustment range  
AGC error (I, Q signal levels)  
54 to 85, in steps of 1  
dB  
RF input between –75 to –20 dBm. AGC_RESET  
used. AGC delay registers (0x05) at default values.  
a) Random (varies each AGC cycle)  
–3  
–1  
–1  
–
–
–
3
1
1
dB  
dB  
dB  
b) Slow (varies with V , Temperature).  
CC  
c) Static (fixed, part to part)  
DC cancellation time  
(after AGCRESET)  
With constant RF input during this time. Note 3.  
a) DC offset < 50% of output signal level  
b) DC offset <10% of output signal level  
–
–
–
–
8
µs  
µs  
13  
TX to RX switching time  
Output signal within 1 dB of final value,  
–
3
3.5  
µs  
frequency error within 25 ppm of final value. Note 3.  
Noise Figure  
Less than the piece-wise linear interpolation. Note 3.  
(Incl balun+matching)  
P
input  
=
–85 dBm (LNA in high gain mode)  
–75 dBm  
–
–
–
–
7.5  
7.5  
24  
9
dB  
dB  
dB  
dB  
9
–60 dBm (LNA in low gain mode)  
–45 dBm  
25  
25  
24  
Input IP3  
(50 Ω source resistance)  
2 interfering tones of power P  
and 23 MHz offsets from LO.  
each, at 13  
–5  
1
–
dBm  
interferer  
IP3 to be more than the piece-wise linear  
interpolation:  
P
= –39 dBm  
interferer  
1 dB compression of wanted signal  
Desens by jammer  
Including matching, receiver at minimum gain.  
–10  
–
0
–
–
1
dBm  
dB  
–45 dBm wanted signal at 1 MHz offset, +40 dBc  
jammer at 25 MHz offset. Note 3.  
10  
2002 Nov 04  
1...78910111213...34

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