Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
streams. In this case, integrated FIR–DACS provide additional
filtering. The data streams are sampled with the reference clock. For
timing specifications, please see the transmitter parameters section.
6.7 AGC Handshake
On the digital input pin AGCRESET, a 0-to-1 transition clears
AGCSET output to logic 0 and starts the AGC cycle. At the end of
the AGC settling, the AGCSET output is asserted to logic 1. The
AGCRESET input can then be reset to logic 0. At any time in the
RECEIVE mode the AGC can be forced to the maximum gain by
giving the AGCRESET signal as described, but by additionally
re-setting it to logic 0 within 1 µs. The AGCSET indication is not
given in this case and the receiver settling time is 3 µs. The channel
filters will be set to have a lower cut-off of 1 MHz. For a timing
diagram, please see the receiver parameters section.
The wide band IQ upconverter includes spectral shaping
th
reconstruction filters (4 order low-pass Butterworth with 9.75 MHz
3 dB upper cut-off frequency).
At +8 dBm maximum transmitter output level the out-of-band (FCC
forbidden band) spurious signal power is less than –77 dBc
(integrated over 1 MHz with a 100 kHz resolution bandwidth) for the
1
11 Msymbols/sec CCK modulation (footnote ). This implies that the
spectral regrowth is dominated by any external PA that may be used
to boost the transmission power level.
6.8 RSSI
The Receive Signal Strength Indicator (RSSI) is implemented as an
error signal comparing the signal level at the Rx output to the
In analog mode, it is assumed that the input baseband IQ signals as
delivered from the Baseband IC are pulse shaped.
nominal value of 500 mV
. It has a –10 dBc to +10 dBc
peak,differential
operational range relative to the nominal signal level. Since the
RSSI acts on the modulated RF signal envelope that is extracted
from the baseband I and Q signals, it includes DC offsets, and will
therefore show transient decaying errors when the AC coupling
lower cut-off frequency is changed.
By using the on-chip calibration loop, the transmitter Carrier
Leakage can be reduced to levels far less than required by the
standard. An RF power meter detects the LO level, converts it into a
digital signal and a state machine determines the compensation
values which are fed through a DAC directly to the IQ inputs. This
mode is activated by setting the IC into the DCALIB mode by means
of 3-wire bus programming. This calibration is designed to
compensate for any DC offsets delivered by the ADCs on the
Baseband IC. The DCALIB cannot be used when the IC is using the
digital-input Tx mode.
The RSSI signal reflects on a logarithmic scale the amplitude of the
instantaneous modulated RF signal (envelope). The RSSI signal is
filtered by a low-pass filter with 0.5 MHz upper cut-off frequency.
The SA2400A receiver is designed to give at least –10 dBc RSSI at
maximum gain, when there is no signal present, i.e., with only
thermal noise. However, due to process spreads (e.g., gain, noise
figure, IQ low-pass filter bandwidth, etc.), the RSSI may show higher
than –10 dBc. In case a calibration is required for setting this noise
power to –10 dBc, the AGC’s maximum gain (GMAX) can be
changed in the range of 85 to 54 dB in steps of 1 dB via register
settings. The programmed value of maximum gain is never altered
by the AGC settling or by forcing the AGC to maximum gain. Only
the RXMGC mode can set the AGC gain to values higher than
GMAX. The RXMGC mode does not change the value of GMAX.
The IQ gain and phase imbalance, reconstruction filter roll-off and
in-channel noise produce a modulation EVM of less than 12% for
11 Msymbols/sec QPSK. The transmitter has two switched outputs,
one with –1.5 dBm output power and the other one with +8 dBm
output power. The input pin TX_HI is used to select between the two
RF output ports.
The 8 dBm output port is differential and is designed to work
seamlessly (no external filtering required) with the SA2411 power
amplifier.
Upon entering the Tx mode, the ramping up of the RF Tx signal is
delayed by an internal power ramping circuit. The ramping up time is
fixed, while the delay prior to ramping up can be programmed by
register settings.
6.9 Receiver blocking immunity
The receiver is designed to exceed the IEEE802.11 specifications
for the blocking and intermodulation. It can accept continuous or
randomly pulsed interfering single- or multi-tone signals that are
more than 35 dB stronger than the wanted signal, and up to
–10 dBm of interference level. The spurious I and Q outputs are
maintained to smaller than –20 dBc of the wanted signal level.
Note: When switching out of the Transmit mode (either into Receive
mode by transition on TXRX pin, or into another mode by 3-wire
programming), the reference clock input (pins XTAL_1 and XTAL_2)
needs to be active since a digital timer is being used.
6.10 Transmitter and IQ upconverter
The transmitter inputs are designed to be driven from a Baseband
IC in one of two modes: a) in analog mode, differential I and Q
inputs expect current signals driven by DACs in the Baseband IC; or
b) in digital mode, single-ended inputs expect two binary data
6.11 Reference current and voltage outputs
The IC provides a temperature-constant reference current of 1 mA
or 300 µA (selectable), active in Tx mode, as well as a 2.5 V
reference voltage.
1.
For a CCK signal, the peak signal power is 21.7 dB lower than the total power integrated over the 22 MHz band. The SA2400A guarantees better than 56 dBc
suppression of the second sidelobe (greater than 22 MHz frequency offset). Consequently, the power level in the forbidden bands is at least 77 dBc below the transmitted
integrated power.
7
2002 Nov 04
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