A d v a n c e I n f o r m a t i o n
Figure 28. Mode Register .................................................. 122
Read-Only Operations–S29GL512N Only ..................................................80
Read-Only Operations–S29GL256N Only .................................................. 81
Read-Only Operations–S29GL128N Only ..................................................82
Figure 11. Read Operation Timings....................................... 83
Figure 12. Page Read Timings.............................................. 83
Hardware Reset (RESET#) .............................................................................. 84
Figure 13. Reset Timings..................................................... 84
Erase and Program Operations–S29GL512N Only .................................. 85
Figure 29. Mode Register UpdateTimings (UB#, LB#, OE# are Don’t
Care) ............................................................................. 122
Figure 30. Deep Sleep Mode - Entry/Exit Timings (for 64M)... 123
Figure 31. Deep Sleep Mode - Entry/Exit Timings
(for 32M and 16M)........................................................... 123
pSRAM Type 7
Erase and Program Operations–S29GL256N Only .................................86
Erase and Program Operations–S29GL128N Only .................................. 87
Figure 14. Program Operation Timings.................................. 88
Figure 15. Accelerated Program Timing Diagram .................... 88
Figure 16. Chip/Sector Erase Operation Timings..................... 89
Figure 17. Data# Polling Timings
(During Embedded Algorithms)............................................ 90
Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 91
Figure 19. DQ2 vs. DQ6...................................................... 91
Alternate CE# Controlled Erase and Program Operations–
S29GL512N Only ................................................................................................ 92
Alternate CE# Controlled Erase and Program Operations–
S29GL256N Only ................................................................................................93
Alternate CE# Controlled Erase and Program Operations–
S29GL128N Only ................................................................................................ 94
Figure 20. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.............................................................. 95
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 95
Erase And Programming Performance . . . . . . . 96
TSOP Pin and BGA Package Capacitance . . . . . 96
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Functional Description . . . . . . . . . . . . . . . . . . . . 128
Power Down ......................................................................................................128
Power Down Program Sequence ................................................................129
Address Key ........................................................................................................129
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 130
Package Capacitance . . . . . . . . . . . . . . . . . . . . . 130
Read Operation .................................................................................................132
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .134
Write Operation ...............................................................................................134
Power Down Parameters ...............................................................................135
Other Timing Parameters ............................................................................... 135
AC Test Conditions .........................................................................................136
AC Measurement Output Load Circuit .....................................................136
Figure 32. AC Output Load Circuit ...................................... 136
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .137
Read Timings ....................................................................................................... 137
Figure 33. Read Timing #1 (Baisc Timing)........................... 137
Figure 34. Read Timing #2 (OE# Address Access................. 137
Figure 35. Read Timing #3 (LB#/UB# Byte Access).............. 138
Figure 36. Read Timing #4 (Page Address Access after CE1# Control
Access for 32M and 64M Only)........................................... 138
Figure 37. Read Timing #5 (Random and Page Address Access for
32M and 64M Only).......................................................... 139
Write Timings ....................................................................................................139
Figure 38. Write Timing #1 (Basic Timing) .......................... 139
Figure 39. Write Timing #2 (WE# Control).......................... 140
Figure 40. Write Timing #3-1
pSRAM Type 1
Functional Description . . . . . . . . . . . . . . . . . . . . . 97
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 97
Timing Test Conditions . . . . . . . . . . . . . . . . . . . 103
Output Load Circuit ........................................................................................104
Figure 21. Output Load Circuit ........................................... 104
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . 104
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 105
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 116
(WE#/LB#/UB# Byte Write Control)................................... 140
Figure 41. Write Timing #3-2
Read Cycle ...........................................................................................................116
Figure 22. Timing of Read Cycle (CE# = OE# = VIL, WE# = ZZ# =
VIH)................................................................................ 116
Figure 23. Timing Waveform of Read Cycle
(WE#/LB#/UB# Byte Write Control)................................... 141
Figure 42. Write Timing #3-3
(WE#/LB#/UB# Byte Write Control)................................... 141
Figure 43. Write Timing #3-4
(WE# = ZZ# = VIH) ......................................................... 117
Figure 24. Timing Waveform of Page Mode Read Cycle (WE# = ZZ#
= VIH) ............................................................................ 118
Write Cycle .........................................................................................................119
Figure 25. Timing Waveform of Write Cycle (WE# Control, ZZ# =
VIH)................................................................................ 119
Figure 26. Timing Waveform of Write Cycle (CE# Control, ZZ# =
(WE#/LB#/UB# Byte Write Control)................................... 142
Read/Write Timings .........................................................................................142
Figure 44. Read/Write Timing #1-1 (CE1# Control).............. 142
Figure 45. Read / Write Timing #1-2
(CE1#/WE#/OE# Control) ................................................ 143
Figure 46. Read / Write Timing #2 (OE#, WE# Control)........ 143
Figure 47. Read / Write Timing #3
(OE#, WE#, LB#, UB# Control)......................................... 144
Figure 48. Power-up Timing #1 ......................................... 144
Figure 49. Power-up Timing #2 ......................................... 145
Figure 50. Power Down Entry and Exit Timing...................... 145
Figure 51. Standby Entry Timing after Read or Write............ 145
Figure 52. Power Down Program Timing (for 32M/64M Only). 146
VIH)................................................................................ 119
Figure 27. Timing Waveform of Page Mode
Write Cycle (ZZ# = VIH) ................................................... 120
Partial Array Self Refresh (PAR) ...................................................................120
Temperature Compensated Refresh (for 64Mb) .....................................121
Deep Sleep Mode ...............................................................................................121
Reduced Memory Size (for 32M and 16M) ..................................................121
Other Mode Register Settings (for 64M) ....................................................121
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 147
December 7, 2004 S71GL512_256_128NB0_00_A1
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