Datasheet > S71GL064NB0BHW0K0

S71GL064NB0BHW0K0

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	317K
描述
Memory IC

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数据手册

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S71GL064NB0BHW0K0 数据手册

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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

4. Pin Description

A21–A0

DQ15–DQ0

CE1#f

Description

22 Address Inputs (Common and Flash only) (A20-A0 for the S71GL032N)

16 Data Inputs/Outputs (Common)

Chip Enable (Flash)

CE1#s

CE2s

Chip Enable 1 (pSRAM/SRAM)

Chip Enable 2 (pSRAM/SRAM)

OE#

Output Enable (Common)

WE#

Write Enable (Common)

RY/BY#

UB#

Ready/Busy Output (Flash 1)

Upper Byte Control (pSRAM/SRAM)

Lower Byte Control (pSRAM/SRAM)

Hardware Reset Pin, Active Low (Flash)

Hardware Write Protect/Acceleration Pin (Flash)

LB#

RESET#

WP#/ACC

Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage

supply tolerances)

V_CC

V_CCS

V_SS

pSRAM/SRAM Power Supply

Device Ground (Common)

Not Connected. No device internal signal is connected to the package connector nor is there any

future plan to use the connector for a signal. The connection may safely be used for routing space for

a signal on a Printed Circuit Board (PCB).

S71GL-N Based MCPs

S71GL-N_00_08 May 6, 2013

1...3 4 567 8 9 10

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