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S70GL02GP11FFCR13 PDF预览

S70GL02GP11FFCR13

更新时间: 2024-11-27 15:50:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路
页数 文件大小 规格书
11页 462K
描述
Flash, 128MX16, PBGA64, 13 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-64

S70GL02GP11FFCR13 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:LBGA,Reach Compliance Code:compliant
ECCN代码:3A991.B.1.AHTS代码:8542.32.00.51
风险等级:5.41备用内存宽度:8
JESD-30 代码:R-PBGA-B64长度:13 mm
内存密度:2147483648 bit内存集成电路类型:FLASH
内存宽度:16功能数量:1
端子数量:64字数:134217728 words
字数代码:128000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:128MX16封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED编程电压:3 V
认证状态:Not Qualified座面最大高度:1.4 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:11 mmBase Number Matches:1

S70GL02GP11FFCR13 数据手册

 浏览型号S70GL02GP11FFCR13的Datasheet PDF文件第2页浏览型号S70GL02GP11FFCR13的Datasheet PDF文件第3页浏览型号S70GL02GP11FFCR13的Datasheet PDF文件第4页浏览型号S70GL02GP11FFCR13的Datasheet PDF文件第5页浏览型号S70GL02GP11FFCR13的Datasheet PDF文件第6页浏览型号S70GL02GP11FFCR13的Datasheet PDF文件第7页 
S70GL02GP  
2 Gbit, 3V Page Mode  
S70GL-P MirrorBit® Flash  
General Description  
The Cypress S70GL02GP 2 Gbit Mirrorbit Flash device is fabricated on 90-nm process technology. This device offers a fast page  
access time of 25 ns with a corresponding random access time of 110 ns. It features a Write Buffer that allows a maximum of 32  
words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard single byte/word  
programming algorithms. This makes the device an ideal product for today’s embedded applications that require higher density,  
better performance and lower power consumption.  
This document contains information for the S70GL02GP device, which is a dual die stack of two S29GL01GP die. For detailed  
specifications, refer to the discrete die datasheet provided in Table 1.  
Table 1. Affected Documents/Related Documents  
Title  
Publication Number  
S29GL01GP, S29GL512P, S29GL256P, S29GL128P  
1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit  
Process Technology  
002-00886  
Distinctive Characteristics  
Two 1024 Mbit (S29GL01GP) in a single 64-ball Fortified-  
BGA package (see S29GL01P datasheet for full  
specifications)  
Suspend and Resume commands for Program and Erase  
operations  
Write operation status bits indicate program and erase  
Single 3V read/program/erase (3.0V - 3.6V)  
90 nm MirrorBit process technology  
8-word/16-byte page read buffer  
operation completion  
Unlock Bypass Program command to reduce programming  
time  
Support for Common Flash Interface (CFI)  
32-word/64-byte write buffer reduces overall programming  
time for multiple-word writes  
Persistent and Password methods of Advanced Sector  
Protection  
Secured Silicon Sector region  
WP#/ACC input  
– 128-word/256-byte sector for permanent, secure  
identification through an 8-word/16-byte random Electronic  
Serial Number  
– Can be programmed and locked at the factory or by the  
customer  
– Accelerates programming time (when VACC is applied) for  
greater throughput during system production  
– Protects first or last sector of each die, regardless of sector  
protection settings  
Uniform 64Kword/128KByte Sector Architecture  
– S70GL02GP: two thousand forty-eight sectors  
100,000 erase cycles per sector typical  
20-year data retention typical  
Hardware reset input (RESET#) resets device  
Ready/Busy# output (RY/BY#) detects program or erase  
cycle completion  
Offered Packages  
– 64-ball Fortified BGA  
Cypress Semiconductor Corporation  
Document Number: 002-01338 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 16, 2016  

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