TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com
SPNS141–MARCH 2010
TMS570LS Series 16/32-BIT RISC Flash Microcontroller
Check for Samples: TMS570LS20216, TMS570LS20206, TMS570LS10216, TMS570LS10206, TMS570LS10116, TMS570LS10106
1 TMS570LS Series 16/32-BIT RISC Flash Microcontroller
1.1 Features
12
• High-Performance Automotive Grade
• Communication Interfaces
Microcontroller for Safety Critical Applications
– Certified for use in SIL3 Applications
– Dual CPU’s running in Lockstep
– Three Multi-buffered Serial Peripheral
Interface (MibSPI) each with:
•
•
•
Four chip selects and one Enable pin
128 buffers with parity
One with parallel mode
– ECC on Flash and SRAM
– CPU and Memory BIST (Built-In Self Test)
– Error Signaling Module (ESM) w/ Error Pin
• ARM® Cortex™-R4F 32-Bit RISC CPU
– Two UART (SCI) interfaces with Local
Interconnect Network Interface (LIN 2.0)
– Three CAN (DCAN) Controller
– Efficient 1.6 DMIPS/MHz with 8-stage
pipeline
– Floating Point Unit with Single/Double
Precision
•
•
Two with 64 mailboxes, one with 32
Parity on mailbox RAM
– Dual Channel FlexRay™ Controller
– Memory Protection Unit (MPU)
– Open Architecture With Third-Party Support
• Operating Features
•
•
8K-Byte message RAM with parity
Transfer Unit with MPU and parity
• High-End Timer (nHET)
– Up to 160-MHz System Clock
– Core Supply Voltage (VCC): 1.5 V
– I/O Supply Voltage (VCCIO): 3.3 V
• Integrated Memory
– 1M-Byte or 2M-Byte Flash with ECC
– 128K-Byte or 160K-Byte RAM with ECC
• Multiple Communication interfaces including
Flexray, CAN, and LIN
– 32 Programmable I/O Channels
– 128 Words High-End Timer RAM with parity
– Transfer Unit with MPU and parity
• Two 12-Bit Multi-Buffered ADCs (MibADC)
– 24 total ADC Input channels
– Each has 64 Buffers with parity
• Trace and Calibration Interfaces
– Embedded Trace Module (ETMR4)
– Data Modification Module (DMM)
– RAM Trace Port (RTP)
• NHET Timer and 2x 12-bit ADC's
• External Memory Interface (EMIF)
– 16bit Data, 22bit Address, 4 Chip Selects
• Common TMS470/570 Platform Architecture
– Consistent Memory Map across the family
– Real-Time Interrupt (RTI) OS Timer
– Vectored Interrupt Module (VIM)
– Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
– Parity on Control Packet Memory
– Parameter Overlay Module (POM)
• On-Chip emulation logic including IEEE 1149.1
JTAG, Boundary Scan and ARM Coresight
components
• Full Development Kit Available
– Development Boards
– Code Composer Studio Integrated
Development Environment (IDE)
– HaLCoGen Code Generation Tool
– HET Assembler and Simulator
– nowFlash Flash Programming Tool
• Packages Supported
– Dedicated Memory Protection Unit (MPU)
• Frequency-Modulated Zero-Pin Phase-Locked
Loop (FMZPLL)-Based Clock Module
– Oscillator and PLL clock monitor
• Up to 115 Peripheral IO pins
– 16 Dedicated GIO - 8 w/ External Interrupts
– Programmable External Clock (ECLK)
1
– 144-Pin Quad Flatpack (PGE) [Green]
– 337-Pin Ball Grid Array (ZWT) [Green]
• Community Resources
– TI E2E Community
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
Copyright © 2010, Texas Instruments Incorporated
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