Datasheet > S3030BH0

S3030BH0

更新时间： 2024-01-30 03:17:14

品牌	Logo	应用领域
AMCC		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
26页	228K
描述
Transceiver, 1-Func, PQFP100, PQFP, TEP, 100 PIN

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技术参数
数据手册

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S3030BH0 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP,	针数：	100
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.83	JESD-30 代码：	R-PQFP-G100
功能数量：	1	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-20 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK
认证状态：	Not Qualified	标称供电电压：	5 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER
温度等级：	OTHER	端子形式：	GULL WING
端子位置：	QUAD	Base Number Matches：	1

S3030BH0 数据手册

PRELIMINARY

SEPE4C/SIFTICMA-T1I/OONC-3 ATM 4-BIT TRANSCEIVER

S3030B

E4/STM-1/OC-3 ATM 4-BIT TRANSCEIVER

FEATURES

GENERAL DESCRIPTION

The S3030B transceiver chip is a fully integrated CMI

encoding transmitter and CMI decoding receiver. The

chip derives high speed timing and data signals for

SONET/SDH or PDH-based equipment. The circuit is

implementedusingAMCC’sprovenPhaseLockedLoop

(PLL) technology. Figure 1a and 1b show typical net-

work applications.

•

Complies with ANSI, Bellcore, and ITU-T

specifications

On-chip high-frequency PLLs for clock

generation and clock recovery

On-chip analog circuitry for transformer

driver and equalization

Supports 139.264 Mbps (E4) and 155.52

Mbps (OC-3) transmission rates

Supports 139.264 Mbps and 155.52 Mbps

Coded Mark Inversion (CMI) interfaces

TTL Reference frequencies of 38.88 MHz

(OC-3) or 34.816 MHz (E4)

Interface to both PECL and TTL logic

Lock detect on clock recovery function —

monitors run length and frequency

4-bit (nibble) system interface

The S3030B has two independent VCOs which are

synchronized to the local NRZ transmitted data and the

received CMI data repectively. The chip can be used

with either a 19.44 MHz or a 38.88 MHz reference clock

when operated in the SONET/SDH OC-3 mode. In E4

mode the chip can be operated with a 17.408 MHz or a

34.816 MHz reference in support of existing system

clockingschemes.On-chipcoded-mark-inversion(CMI)

encoding and decoding is provided for 139.264 Mbps

and 155.52 Mbps interfaces.

•

Low jitter PECL interface

+5v operation

100 PQFP TEP package

Supports both electrical and optical interfaces

The low jitter PECL nibble clock interface guarantees

compliance with the bit-error rate requirements of the

Bellcore, ANSI, and ITU-T standards. The S3030B is

packaged in a 0.65mm pitch 100-pin PQFP TEP.

APPLICATIONS

•

ATM over SONET/SDH

OC-3/STM-1 or E4-based transmission

systems

OC-3/STM-1 or E4 modules

OC-3/STM-1 or E4 test equipment

Section repeaters

Add drop multiplexors

Broadband cross-connects

Fiber optic terminators

The S3030B provides the major active components on-

chip for a coaxial cable interface, including analog

transformer driver circuitry and equalization interface

circuitry. Discrete controls permit separate selection of

CMI or NRZ operation and analog (coaxial copper) or

PECL (optical module) media interfaces. Both line

loopback and diagnostic local loopback operation are

supported.

•

Fiber optic test equipment

Figure 1a. Electrical Interface

COAX

Nibble Data

139/155 Mbps CMI

E4/STM-1/OC-3

OVERHEAD

PROCESSOR

XFMR

S3030B

XCVR

Nibble Data

COAX

139/155 Mbps CMI

XFMR

34.816/38.88 MHz

OSC

Figure 1b. Optical Interface

Nibble Data

139/155 Mbps

E4/STM-1/OC-3

OVERHEAD

PROCESSOR

OTX

S3030B

XCVR

ORX

34.816/38.88 MHz

OSC

12 3 4 5 6 7...26

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