Datasheet > S29XS256RAABHW300

S29XS256RAABHW300

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
71页	2815K
描述
Flash, 16X16, PBGA44, 6.20 X 7.70 MM, LEAD FREE AND HALOGEN FREE, FPBGA-44

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S29XS256RAABHW300 数据手册

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D a t a S h e e t ( A d v a n c e I n f o r m a t i o n )

2. Input/Output Descriptions & Logic Symbol

Table 2.1 identifies the input and output package connections provided on the device.

Table 2.1 Input/Output Descriptions

Symbol

Type

Description

Higher order address lines. Amax = A23 for VS256R, A22 for VS128R.

On the XS256R and XS128R, these inputs can be left unconnected in AADM mode.

Amax – A16

A/DQ15 – A/DQ0

I/O

Multiplexed Address/Data input/output

Flash Chip Enable. Asynchronous relative to CLK.

Output Enable. Asynchronous relative to CLK for the Burst mode.

Write Enable

CE#

OE#

WE#

Input

Supply

I/O

Device Power Supply

Input/Output Power Supply (must be ramped simultaneously with V

)

CCQ

Ground

I/O

Input/Output Ground

SSQ

No Connect No Connected internally

RDY

Output

Ready. Indicates when valid burst data is ready to be read

The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst

mode operation. After the initial word is output, subsequent rising edges of CLK increment the

internal address counter. CLK should remain low during asynchronous access

CLK

Input

Address Valid input. Indicates to device that the valid address is present on the address inputs

(address bits A15 – A0 are multiplexed, address bits Amax – A16 are address only).

AVD#

Input

V = for asynchronous mode, indicates valid address; for burst mode, cause staring address to be

latched on rising edge of CLK.

= device ignores address inputs

RESET#

Input

Hardware Reset. Low = device resets and returns to reading array data.

Accelerated input.

At V , accelerates programming; automatically places device in unlock bypass mode.

Input

At V ,disables all program and erase functions.

Should be at V for all other conditions.

RFU

Reserved

Reserved for future use

S29VS/XS-R MirrorBit^®Flash Family

S29VS_XS-R_00_04 March 10, 2009

1...5 6 789 10 11...71

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与S29XS256RAABHW300相关器件

型号	品牌	获取价格	描述	数据表
S29XS256RAABHW301	CYPRESS	获取价格	Flash, 16X16, PBGA44, 6.20 X 7.70 MM, LEAD FREE AND HALOGEN FREE, FPBGA-44
S29XS256RABBHI000	CYPRESS	获取价格	Flash, 32MX8, 80ns, PBGA44, 7.70 X 6.20 MM, 1 MM HEIGHT, HALOGEN FREE AND LEAD FREE, FBGA-
S29XS256RABBHI003	CYPRESS	获取价格	Flash, 32MX8, 80ns, PBGA44, 7.70 X 6.20 MM, 1 MM HEIGHT, HALOGEN FREE AND LEAD FREE, FBGA-
S29XS256RABBHW000	SPANSION	获取价格	Flash, 32MX8, 80ns, PBGA44, 7.70 X 6.20 MM, 1 MM HEIGHT, HALOGEN FREE AND LEAD FREE, FBGA-
S29XS256RABBHW001	CYPRESS	获取价格	Flash, 16X16, PBGA44, 6.20 X 7.70 MM, LEAD FREE AND HALOGEN FREE, FPBGA-44
S29XS256RABBHW010	CYPRESS	获取价格	Flash, 32MX8, 80ns, PBGA44, FBGA-44
S29XS256RABBHW10	SPANSION	获取价格	Flash, 16MX16, 80ns, PBGA44, 6.20 X 7.70 MM, LEAD FREE AND HALOGEN FREE, FPBGA-44
S29XS256RABBHW13	SPANSION	获取价格	Flash, 16MX16, 80ns, PBGA44, 6.20 X 7.70 MM, LEAD FREE AND HALOGEN FREE, FPBGA-44
S29XS256RABBHW300	CYPRESS	获取价格	Flash, 16X16, PBGA44, 6.20 X 7.70 MM, LEAD FREE AND HALOGEN FREE, FPBGA-44
S-29XX0A	SII	获取价格	CMOS SERIAL EEPROM