128 Mb/256 Mb/512 Mb/1 Gb GL-S MIRRORBIT™ Flash
Parallel, 3.0 V
Address space maps
2
Address space maps
There are several separate address spaces that may appear within the address range of the flash memory device.
One address space is visible (entered) at any given time.
• Flash memory array: the main non-volatile memory array used for storage of data that may be randomly
accessed by asynchronous read operations.
• ID/CFI: a memory array used for Infineon factory programmed device characteristics information. This area
contains the device identification (ID) and common flash interface (CFI) information tables.
• Secure silicon region (SSR): a one time programmable (OTP) non-volatile memory array used for Infineon factory
programmed permanent data, and customer programmable permanent data.
• Lock register: an OTP non-volatile word used to configure the ASP features and lock the SSR.
• Persistent protection bits (PPB): a non-volatile flash memory array with one bit for each sector. When
programmed, each bit protects the related sector from erasure and programming.
• PPB lock: a volatile register bit used to enable or disable programming and erasure of the PPB bits.
• Password: an OTP non-volatile array used to store a 64-bit password used to enable changing the state of the
PPB lock bit when using password mode sector protection.
• Dynamic protection bits (DYB): a volatile array with one bit for each sector. When set, each bit protects the
related sector from erasure and programming.
• Status register: a volatile register used to display embedded algorithm status.
• Data polling status: a volatile register used as an alternate, legacy software compatible, way to display
embedded algorithm status.
• ECC status: provides the status of any error detection or correction action taken when reading the selected page.
The main flash memory array is the primary and default address space but, it may be overlaid by one other
address space, at any one time. Each alternate address space is called an address space overlay (ASO).
Each ASO replaces (overlays) the entire flash device address range. Any address range not defined by a particular
ASO address map, is reserved for future use. All read accesses outside of an ASO address map returns non-valid
(undefined) data. The locations will display actively driven data but the meaning of whatever 1’s or 0’s appear
are not defined.
There are four device operating modes that determine what appears in the flash device address space at any
given time:
• Read mode
• Data polling mode
• Status register (SR) mode
• Address space overlay (ASO) mode
In read mode the entire flash memory array may be directly read by the host system memory controller. The
memory device embedded algorithm controller (EAC), puts the device in read mode during power-on, after a
hardware reset, after a command reset, or after an embedded algorithm (EA) is suspended. Read accesses and
command writes are accepted in read mode. A subset of commands are accepted in read mode when an EA is
suspended.
While in any mode, the status register read command may be issued to cause the status register ASO to appear
at every word address in the device address space. In this status register ASO Mode, the device interface waits for
a read access and, any write access is ignored. The next read access to the device accesses the content of the
status register, exits the status register ASO, and returns to the previous (calling) mode in which the status
register read command was received.
Datasheet
7
001-98285 Rev. *T
2023-07-17
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