Datasheet > S29GL512S11FHIV23

S29GL512S11FHIV23

更新时间： 2023-12-06 19:46:15

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
118页	1459K
描述
High Performance Page Mode

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128 Mb/256 Mb/512 Mb/1 Gb GL-S MIRRORBIT™ Flash

Parallel, 3.0 V

Product overview

The GL-S family consists of 128-Mb to 1-Gb, 3.0 V core, versatile I/O, non-volatile, flash memory devices. These

devices have a 16-bit (word) wide data bus and use only word boundary addresses. All read accesses provide

16 bits of data on each bus transfer cycle. All writes take 16 bits of data from each bus transfer cycle.

DQ15–DQ0

RY/BY#

Sector Switches

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

WP#

State

Control

Command

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

Detector

Timer

Cell Matrix

X-Decoder

**–A0

Max

** A_MAXGL01GS = A25, A_MAXGL512S = A24, A_MAXGL256S = A23, A_MAXGL128S = A22

Figure 1

Block diagram

The GL-S family combines the best features of eXecute-In-Place (XIP) and data storage flash memories. This

family has the fast random access of XIP flash along with the high density and fast program speed of Data Storage

flash.

Read access to any random location takes 90 ns to 120 ns depending on device density and I/O power supply

voltage. Each random (initial) access reads an entire 32-byte aligned group of data called a page. Other words

within the same page may be read by changing only the low order 4 bits of word address. Each access within the

same page takes 15 ns to 30 ns. This is called page mode read. Changing any of the higher word address bits will

select a different page and begin a new initial access. All read accesses are asynchronous.

Datasheet

001-98285 Rev. *T

2023-07-17

1 2 3 456 7 8...118

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