S29CD032J
S29CD016J
S29CL032J
S29CL016J
Document Title: S29CD032J, S29CD016J, S29CL032J, S29CL016J, 32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/
Write, Burst Flash
Document Number: 002-00948
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
Global
Removed “Preliminary”
Changed all instances of VCCQ to VIO
Distinctive Characteristics Removed “or without” (wrap around) from Programmable
Burst Interface bullet
Performance Characteristics Added notice to refer to programming best practices
application note for 32 Mb devices.
Ordering Information
Added S29CL032J to valid OPN diagram.
Corrected valid combinations table.
Input/Output Descriptions and Logic Symbols
Subscript CC for VCC, IO for VIO, SS for VSS in table.
Changed type for VIO to “Supply”
Changed type for VSS to “Supply”
Block Diagram
Removed DQmax-DQ0 label from inputs to Burst Address Counter and Address Latch.
Removed Amax-A0 label from I/O Buffers.
Table: S29CD016J/CL016J (Top Boot) Sector and Memory Address Map
Changed Note 2 to refer to Bank 0 and 1 instead of Bank 1 and 2.
Table: 32-Bit Linear and Burst Data Order
03/30/2009
Removed “x16”
Removed “A0:A-1” from Output Data Sequence column for Four Linear Data Transfers.
Removed “A1:A-1” from Output Data Sequence column for Eight Linear Data Transfers.
Programming Added notice to refer to programming best practices application note for
32 Mb devices.
Table: DC Characteristic, CMOS Compatible
Changed Max ICCB for S29CL-J to 90 mA.
Table: Burst Mode for 32 Mb and 16 Mb
Corrected values for tBDH with separate values for 16Mb and 32Mb.
Added tWADVS parameter to table.
**
-
RYSU
Figure: Synchronous Command Write/ Read Timing
Added timing definition for tWADVS.
Table: Erase/Program Operations
Appended “from WE# Rising Edge” to tAH description.
Changed tAH Min to 11.75 ns.
Figure: Program Operation Timings Updated timing diagram to reflect new tAH
value.
Figure: Chip/Sector Erase Operation Timings
Updated timing diagram to reflect new tAH value.
Table: Alternate CE# Controlled Erase/Program Operations
Removed tWADVS parameter.
Product Overview Removed “or without”.
Table: Device Bus Operation Changed “X” to “H” under CLK column for CE# row.
Accelerated Program and Erase Operations
Removed all mention of accelerated erase.
Unlock Bypass Removed mention of unlock bypass sector erase.
Simultaneous Read/Write Added in warning to indicate restrictions on Simultaneous
03/30/2009 Read/Write conditions.
VCC and VIO Power-up And Powerdown Sequencing
Added reference to timing section.
Standby Mode Changed Vcc ± 0.2V to Vcc ± 10%.
Figure: Test Setup Removed Note “Diodes are IN3064 or equivalent”.
Table: Alternate CE# Controlled Erase/Program Operations
Corrected values for tDH with separate values for 16 Mb and 32 Mb.
Table: Memory Array Command Definitions (x32 Mode)
Cleaned up Notes.
Document Number: 002-00948 Rev. *C
Page 72 of 74
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