S29AL008J
8-Mbit (1M × 8-Bit/512K × 16-Bit), 3 V,
Boot Sector Flash
Distinctive Characteristics
Architectural Advantages
Performance Characteristics
Single Power Supply Operation
High Performance
– Full voltage range: 2.7 to 3.6 volt read and write operations
for battery-powered applications
– Access times as fast as 55 ns
– Extended temperature range (–40°C to +125°C)
– Automotive AEC-Q100 Grade 3 (–40 °C to +85 °C)
– Automotive AEC-Q100 Grade 1 (–40 °C to +125 °C)
Ultra Low Power Consumption (typical values at 5 MHz)
– 0.2 µA Automatic Sleep mode current
– 0.2 µA standby mode current
Manufactured on 110 nm Process Technology
– Fully compatible with 200 nm S29AL008D
Secured Silicon Sector region
– 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random Electronic
Serial Number accessible through a command sequence
– May be programmed and locked at the factory or by the
customer
– 7 mA read current
– 20 mA program/erase current
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
Flexible Sector Architecture
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64
Kbyte sectors (byte mode)
– One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32
Kword sectors (word mode)
Package Options
48-ball Fine-pitch BGA
48-pin TSOP
Sector Group Protection Features
– A hardware method of locking a sector to prevent any
program or erase operations within that sector
– Sectors can be locked in-system or via programming
equipment
– Temporary Sector Unprotect feature allows code changes
in previously locked sectors
Software Features
CFI (Common Flash Interface) Compliant
– Provides device-specific information to the system,
allowing host software to easily reconfigure for different
Flash devices
Erase Suspend/Erase Resume
Unlock Bypass Program Command
– Suspends an erase operation to read data from, or
program data to, a sector that is not being erased, then
resumes the erase operation
– Reduces overall programming time when issuing multiple
program command sequences
Top or Bottom Boot Block Configurations Available
Data# Polling and Toggle Bits
Compatibility with JEDEC standards
– Pinout and software compatible with single-power supply
Flash
– Provides a software method of detecting program or erase
operation completion
– Superior inadvertent write protection
Hardware Features
Ready/Busy# Pin (RY/BY#)
– Provides a hardware method of detecting program or
erase cycle completion
Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
WP# input pin
– For boot sector devices: at VIL, protects first or last
16 Kbyte sector depending on boot configuration (top boot
or bottom boot)
Cypress Semiconductor Corporation
Document Number: 002-00778 Rev. *P
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198 Champion Court
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San Jose, CA 95134-1709
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408-943-2600
Revised April 11, 2018