Part Number S2202
Revision 1.0 - February 25, 2000
APPLICATION NOTE
S2202
Application Note and Reference Diagrams
Introduction
This document is intended to assist customers in using AMCC's S2202 dual channel physical layer device. Details
concerning application information, circuit design, layout, and component selection are provided to help insure first-
pass success in implementing a functional design with optimal signal quality. This document should be used in con-
junction with the product device specification. An elementary knowledge of high-speed printed circuit layout
techniques is assumed. Contact your local AMCC Field Applications Engineer or Regional Sales Manager to dis-
cuss any questions or concerns you may have.
Serial Input / Output Connections
Figure 1 shows the basic coupling termination scheme for the S2202 high-speed serial inputs. The serial inputs are
µ
µ
internally DC biased at VCC - 1.3 V. Recommended external connections include 0.01 F (or 0.1 F) AC coupling
capacitors and a line-to-line termination resistor. The termination resistor is required for lines lengths greater than 1
cm, which exhibit transmission line effects at gigabit speeds. The termination must match the characteristic imped-
Ω
ance of the differential lines to minimize signal reflections. The 100 value shown assumes characteristic line
Ω
Ω
Ω
impedance of 50 (if the lines are 75 , the line-to-line termination resistor should be 150 ). The AC coupling
capacitors allow the DC bias point to be set internally by the input stage. The DC bias can be set externally by
implementing a resistor divider network on each line, but this is not recommended since it increases the part count
and does not provide performance improvement.
Ω
Figure 2 shows the connection diagram for high-speed serial outputs. The 4.5 k pull-down resistors set the drive
current of the output stage. The outputs of the S2202 have internal pull-down resistors integrated into the output
Ω
macro. For Gigabit Ethernet applications the 4.5 k pull-down resistors can be omitted. This will slightly reduce sig-
nal swing and slightly degrade signal integrity, but the part easily passes IEEE 802.3z requirements without the
external pull-down resistors in place. For serial backplane applications, where greater eye opening into the
receiver results in lower bit error rates, the pull-down resistor may be included or removed as a system trade-off;
ease of layout vs. slightly better signal integrity.
Figure 3 shows an input offset voltage biasing configuration, which should be implemented in the event that the
Ω
input is unused and may be subjected to noise. The 220 k pull-down resistor offsets the input by approximately
60 mV, insuring that noise signals with amplitude less than 60 mV will not cause the input to chatter.
At a signal rate of 1.25 Gbps the output stage can drive more than 25 m of Twinax cable directly, with or without the
Ω
external 4.5 k pull-down resistors.
1