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S1300AAMA-FREQ PDF预览

S1300AAMA-FREQ

更新时间: 2024-11-19 08:03:03
品牌 Logo 应用领域
百利通 - PERICOM 机械振荡器
页数 文件大小 规格书
3页 2985K
描述
LVCMOS Output Clock Oscillator, 1.5MHz Min, 28.6363MHz Max

S1300AAMA-FREQ 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:compliant
ECCN代码:EAR99风险等级:5.7
最大控制电压:3 V最小控制电压:0.3 V
最长下降时间:9 ns频率调整-机械:NO
频率偏移/牵引率:70 ppm频率稳定性:20%
JESD-609代码:e0线性度:5%
安装特点:THROUGH HOLE MOUNT最大工作频率:28.6363 MHz
最小工作频率:1.5 MHz最高工作温度:70 °C
最低工作温度:振荡器类型:LVCMOS
输出负载:30 pF物理尺寸:21mm x 13mm x 5.08mm
最长上升时间:9 ns标称供电电压:3.3 V
表面贴装:NO最大对称度:45/55 %
端子面层:Tin/Lead (Sn/Pb)Base Number Matches:1

S1300AAMA-FREQ 数据手册

 浏览型号S1300AAMA-FREQ的Datasheet PDF文件第2页浏览型号S1300AAMA-FREQ的Datasheet PDF文件第3页 
SaRonix  
Voltage Controlled Crystal Oscillator  
3.3V, LVCMOS  
S1300 / S1309 / ST1300 / ST1309 Series  
Technical Data  
Frequency Range:  
1.5 MHz to 28.6363 MHz  
Frequency Stability:  
2ꢀ, 25 or 5ꢀppm over all conditionsꢁ operating  
temperature, voltage change, load change, calibration  
tolerance, shock and vibration, with V = 1.65V  
C
Aging @ 25°C:  
3ppm max per year, 1ꢀppm max for 1ꢀ years  
Temperature Range:  
Operatingꢁ  
Storageꢁ  
ꢀ to +7ꢀ°C or -4ꢀ to +85°C  
-55 to +125°C  
Supply Voltage:  
Recommended Operatingꢁ  
3.3V 1ꢀ0  
1ꢀmA typ, 15mA max  
Supply Current:  
Output Drive:  
ACTUAL SIZE  
Description  
Symmetryꢁ  
Rise & Fall Timesꢁ  
Logic ꢀꢁ  
45/550 max @ 5ꢀ0 V  
DD  
9ns max 2ꢀ0 to 8ꢀ0 V  
DD  
A 3.3V, voltage controlled crystal oscil-  
lator with output logic levels compatible  
with LVCMOS and LVTTL logic fami-  
lies. The series is designed with excellent  
Jitter characteristics which makes it ideal  
for use in Telecom and Datacom applica-  
tions. True SMD DIL versions for IR  
reflow are available, select option "S" in  
part number builder. See separate data  
sheet for SMD package dimensions.  
1ꢀ0 V  
9ꢀ0 V  
3ꢀpF  
max  
min  
DD  
DD  
Logic 1ꢁ  
Loadꢁ  
Jitterꢁ  
3.5ps max RMS period jitter  
Pull Characteristics:  
Input Impedance (pin 1)ꢁ  
Frequency Response (-3dB)ꢁ  
Pullabilityꢁ  
5ꢀKmin  
1ꢀ kHz min  
5ꢀ, 7ꢀ, 1ꢀꢀppm APRꢂ min  
ꢀ.3 to 3.ꢀV  
Frequency Increases when Control Voltage Increases  
5 or 1ꢀ0 max  
1.65V  
Control Voltageꢁ  
Transfer Functionꢁ  
Linearityꢁ  
Applications & Features  
Center Control Voltageꢁ  
Phase-Locked Loop (PLL) Clock and  
DataRecovery, FrequencyTransaltion,  
Frequency Synthesis apps in Video,  
Video Compression, Telephony, and  
LAN/WAN Data Communication  
3.3 Volt operations  
LVCMOS / LVTTL compatible  
3.5ps max RMS period jitter  
Wide range of performance optionsꢁ  
5ꢀ to 1ꢀꢀ ppm APRꢂ  
Mechanical:  
Shockꢁ  
Solderabilityꢁ  
MIL-STD-883, Method 2ꢀꢀ2, Condition B  
MIL-STD-883, Method 2ꢀꢀ3  
MIL-STD-883, Method 2ꢀꢀ4, Condition B2  
MIL-STD-883, Method 2ꢀꢀ7, Condition A  
MIL-STD-2ꢀ2, Method 215  
Terminal Strengthꢁ  
Vibrationꢁ  
Solvent Resistanceꢁ  
Resistance to Soldering Heatꢁ  
MIL-STD-2ꢀ2, Method 21ꢀ, Conditions A, B or C  
( I or J for Gull Wing)  
Environmental:  
Gross Leak Testꢁ  
Fine Leak Testꢁ  
Thermal Shockꢁ  
MIL-STD-883C, Method 1ꢀ14, Condition C  
MIL-STD-883C, Method 1ꢀ14, Condition A2  
MIL-STD-883C, Method 1ꢀ11, Condition A  
MIL-STD-883C, Method 1ꢀꢀ4  
2ꢀ to 5ꢀ ppm Frequency Stability  
Tri-State option  
True SMD for IR reflow available  
Moisture Resistanceꢁ  
Output Waveform  
CMOS  
T
r
T
f
Logic 1  
80%V  
50%V  
20%V  
DD  
DD  
DD  
APR = (VCXO Pull relative to specified Output Frequency) (VCXO Frequency Stability)  
NOTE: APR is inclusive of 10 Years Aging  
Logic 0  
SYMMETRY  
DS-126 REV E  
SaRonix  
www.pericom.com/saronix  

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