RTL8305SB-VD
Datasheet
Table of Contents
RTL8305SB-VD............................................................................................................................................................................ I
RTL8305SB-VD-LF ..................................................................................................................................................................... I
1. GENERAL DESCRIPTION................................................................................................................................................1
2. FEATURES...........................................................................................................................................................................3
3. BLOCK DIAGRAM.............................................................................................................................................................4
4. PIN ASSIGNMENTS ...........................................................................................................................................................5
4.1.
PACKAGE IDENTIFICATION ...........................................................................................................................................5
5. PIN DESCRIPTIONS ..........................................................................................................................................................7
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
5.10.
5.11.
MEDIA CONNECTION PINS............................................................................................................................................7
CONFIGURATION PINS ..................................................................................................................................................7
PORT4 EXTERNAL MAC INTERFACE PINS ....................................................................................................................8
PORT 4 MAC CIRCUIT INTERFACE PIN DEFINITIONS ..................................................................................................11
PORT 4 PHY CIRCUIT INTERFACE PIN DEFINITIONS ...................................................................................................13
MISCELLANEOUS PINS ...............................................................................................................................................15
PORT LED PINS..........................................................................................................................................................16
POWER PINS...............................................................................................................................................................17
SERIAL EEPROM AND SMI PINS...............................................................................................................................18
STRAPPING PINS.........................................................................................................................................................18
PORT STATUS STRAPPING PINS ...................................................................................................................................20
6. REGISTER DESCRIPTIONS ..........................................................................................................................................22
6.1.
6.1.1.
PHY0 TO 4: PHY REGISTER OF EACH PORT...............................................................................................................23
Register0: Control Register..................................................................................................................................23
Register1: Status Register.....................................................................................................................................24
Register4: Auto-Negotiation Advertisement Register...........................................................................................25
Register5: Auto-Negotiation Link Partner Ability Register..................................................................................25
PHY0: EEPROM REGISTER0 ....................................................................................................................................26
Register16: EEPROM Byte0 and 1 Register ........................................................................................................26
Register17: EEPROM Byte2 and 3 Register ........................................................................................................27
Register18~20: EEPROM EthernetID Register For Bytes 4, 5, 6, 7, 8, and 9.....................................................27
Register21: EEPROM Byte10 and 11 Register.....................................................................................................27
Register22: EEPROM Byte12 and 13 Register ....................................................................................................28
PHY1: EEPROM REGISTER1 ....................................................................................................................................29
Register16~23: EEPROM (Byte 14~29) Register ................................................................................................29
Register24~31: EEPROM VLAN (Byte 30~44) Register......................................................................................29
PHY2: PIN & EEPROM REGISTER ............................................................................................................................30
Register16: Pin Register.......................................................................................................................................30
Register17: Pin & EEPROM (Byte 45) Register for VLAN..................................................................................31
PHY3: PORT CONTROL REGISTER..............................................................................................................................33
Register16: Port Control Register........................................................................................................................33
Register17: EEPROM (Byte 46) Register.............................................................................................................34
Register18~20: EEPROM (Byte 47~52) Register ................................................................................................34
6.1.2.
6.1.3.
6.1.4.
6.2.
6.2.1.
6.2.2.
6.2.3.
6.2.4.
6.2.5.
6.3.
6.3.1.
6.3.2.
6.4.
6.4.1.
6.4.2.
6.5.
6.5.1.
6.5.2.
6.5.3.
7. FUNCTIONAL DESCRIPTION.......................................................................................................................................35
7.1.
7.1.1.
SWITCH CORE FUNCTIONAL OVERVIEW.....................................................................................................................35
Application ...........................................................................................................................................................35
Port4.....................................................................................................................................................................35
Port Status Configuration.....................................................................................................................................38
Enable Port...........................................................................................................................................................39
Flow Control ........................................................................................................................................................39
Address Search, Learning, and Aging ..................................................................................................................40
7.1.2.
7.1.3.
7.1.4.
7.1.5.
7.1.6.
5-port 10/100Mbps Single-Chip Dual MII Switch Controller iii
Track ID: JATR-1076-21 Rev. 1.5
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