RTL8305SB-VD
Datasheet
TABLE 54. DIGITAL TIMING CHARACTERISTICS.............................................................................................................................73
TABLE 55. MII&SMI DC TIMING .................................................................................................................................................74
TABLE 56. THERMAL SIMULATION ASSEMBLY DESCRIPTION.........................................................................................................78
TABLE 57. THERMAL SIMULATION CONDITIONS............................................................................................................................78
TABLE 58. THERMAL SIMULATION MATERIAL PROPERTY..............................................................................................................78
TABLE 59. TRANSFORMER VENDORS.............................................................................................................................................81
TABLE 60. ORDERING INFORMATION ............................................................................................................................................88
List of Figures
FIGURE 1. RTL8305SB-VD BLOCK DIAGRAM..............................................................................................................................4
FIGURE 2. PIN ASSIGNMENTS.........................................................................................................................................................5
FIGURE 3. PORT4 OPERATING MODE OVERVIEW .........................................................................................................................37
FIGURE 4. TRADITIONAL APPLICATION ........................................................................................................................................41
FIGURE 5. DUAL MII APPLICATION DIAGRAM .............................................................................................................................42
FIGURE 6. DUAL MII MODE WITH 1 MII-MAC + 1 MII-PHY (100BASE-T UTP) INTERFACES APPLICATION CIRCUIT................42
FIGURE 7. DUAL MII MODE WITH 1 MII-MAC + 1 MII-PHY (100BASE-FX MODE) INTERFACES APPLICATION CIRCUIT ...........43
FIGURE 8. DUAL MII MODE WITH 1 MII-PHY + 1 MII-PHY (100BASE-T UTP) INTERFACES APPLICATION CIRCUIT .................43
FIGURE 9. DUAL MII MODE WITH 1 SNI-PHY + 1 MII-PHY (100BASE-T UTP) INTERFACES APPLICATION CIRCUIT.................44
FIGURE 10. RESET.........................................................................................................................................................................49
FIGURE 11. START AND STOP DEFINITION......................................................................................................................................51
FIGURE 12. OUTPUT ACKNOWLEDGE ............................................................................................................................................51
FIGURE 13. RANDOM READ...........................................................................................................................................................52
FIGURE 14. SEQUENTIAL READ .....................................................................................................................................................52
FIGURE 15. VLAN CONFIGURATION .............................................................................................................................................54
FIGURE 16. EXAMPLE OF VLAN CONFIGURATION FOR DISMEMFILTER .......................................................................................56
FIGURE 17. EXAMPLE OF VLAN CONFIGURATION FOR LEAKY VLAN .........................................................................................57
FIGURE 18. INPUT DROP VS. OUTPUT DROP ..................................................................................................................................60
FIGURE 19. LOOP EXAMPLE ..........................................................................................................................................................60
FIGURE 20. PORT4 LOOPBACK ......................................................................................................................................................62
FIGURE 21. REG. 0.14 LOOPBACK..................................................................................................................................................62
FIGURE 22. FLOATING AND PULL-DOWN OF LED PINS .................................................................................................................63
FIGURE 23. TWO PIN BI-COLOR LED FOR SPD FLOATING OR PULL-HIGH.....................................................................................64
FIGURE 24. TWO PIN BI-COLOR LED FOR SPD PULL-DOWN.........................................................................................................64
FIGURE 25. USING A PNP TRANSISTOR TO TRANSFORM 3.3V INTO 2.5V ......................................................................................65
FIGURE 26. RECEPTION DATA TIMING OF MII/SNI/SMI INTERFACE .............................................................................................74
FIGURE 27. TRANSMISSION DATA TIMING OF MII/SNI/SMI INTERFACE .......................................................................................74
FIGURE 28. JUNCTION TO AMBIENT THERMAL RESISTANCE ..........................................................................................................79
FIGURE 29. JUNCTION TO CASE THERMAL RESISTANCE ................................................................................................................79
FIGURE 30. JUNCTION TO BOARD THERMAL RESISTANCE .............................................................................................................80
FIGURE 31. THERMAL SIMULATION RESULT..................................................................................................................................80
FIGURE 32. UTPAPPLICATION FOR TRANSFORMER WITH CONNECTED CENTRAL TAP ..................................................................81
FIGURE 33. UTPAPPLICATION FOR TRANSFORMER WITH SEPARATE CENTRAL TAP ......................................................................82
FIGURE 34. 100BASE-FX WITH 3.3V FIBER TRANSCEIVER APPLICATION......................................................................................83
FIGURE 35. 100BASE-FX WITH 5V FIBER TRANSCEIVER APPLICATION.........................................................................................84
FIGURE 36. SYSTEM APPLICATION DIAGRAM ................................................................................................................................85
5-port 10/100Mbps Single-Chip Dual MII Switch Controller vii
Track ID: JATR-1076-21 Rev. 1.5
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