Datasheet > RTL8305SB-VD-LF

RTL8305SB-VD-LF

更新时间： 2024-01-28 22:19:04

品牌	Logo	应用领域
瑞昱 - REALTEK		/
页数	文件大小	规格书
95页	1245K
描述
Micro Peripheral IC

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RTL8305SB-VD-LF 数据手册

RTL8305SB-VD

Datasheet

transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any

means without the written permission of Realtek Semiconductor Corp.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document

are trademarks/registered trademarks of their respective owners.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,

including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in

this document or in the product described in this document at any time. This document could include

technical inaccuracies or typographical errors.

USING THIS DOCUMENT

This document is intended for use by the software engineer when programming for Realtek RTL8305SB

Version D controller chips. Information pertaining to the hardware design of products using these chips is

contained in a separate document.

Though every effort has been made to assure that this document is current and accurate, more information

may have become available subsequent to the production of this guide. In that event, please contact your

Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision

Release Date

2003/01/30

2003/02/12

Summary

First release.

1.0

1.1

Modify VLAN feature description.

Add power consumption feature.

Enhance MII/SNI/SMI timing specification.

1.2

1.3

2003/06/10

2004/04/03

Change the crystal and oscillator.

Change VDDAL to RVDD in the all document.

Add TVDD, AVDD, MVDD, and RVDD AC characteristic description.

Add AC characteristic of MAC/PHY mode MII when DISINVERTER is pulled-low.

Correct Figure 6~Figure 9 application diagrams.

Update Table 55 parameters.

Update Figure 25, ‘Using a PNP Transistor to

Transform 3.3V Into 2.5V’.

Pin 42, DISDUALMII: Type changed to I/O.

Update MTXD[3:0]/PRXD[3:0], MTXEN/PRXDV Output Setup and Hold time.

Crystal/Oscillator maximum frequency tolerance, page 65, revised from ±100ppm to

±50ppm.

Correct TCP/IP’s TOS/DiffServ (DS) based priority description in 7.3.8 QoS

Function, page 57.

Update 9.6 Thermal Characteristics, page 78.

Add section 4.1 Package Identification, page 5

Add section 14 Ordering Information, page 88.

1.4

1.5

2004/07/26

2005/11/25

5-port 10/100Mbps Single-Chip Dual MII Switch Controller ii

Track ID: JATR-1076-21 Rev. 1.5

123 4 5 6 7...95

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