Datasheet > RT9088B

RT9088B

更新时间： 2024-04-09 18:59:12

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RT9088B 数据手册

RT9088B

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Note 2. θ_JAis measured under natural convection (still air) at T_A= 25°C with the component mounted on a high effective-

thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θ_JCis measured at the

exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. t_DELAYis the period from EN turn on to V_OUTrising as shown in below diagram. While T_SSis the rising period of V_OUT

the formula used to calculated this rising period is T_SS= (V_OUTx C_OUT)/I_LIM. It's base on the value of output capacitor

C_OUT, the settled output voltage V_OUTand the output current limit I_LIM.

VCNTL

REFOUT

VOUT

= (V

x C ) / I

OUT LIM

OUT

DELAY

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS9088B-00 March 2020

1...3 4 567 8 9...12

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