RT8877C
Functional Pin Description
Pin No.
Pin Name
Pin Function
1, 52, 51, 50
PWM4 to PWM1
PWM Outputs for Channel 1, 2, 3 and 4 of VDD Controller.
VDD Controller On-Time Setting. Connect this pin to the converter input
voltage, Vin, through a resistor, RTON, to set the on-time of UGATE and
also the output voltage ripple of VDD controller.
2
TONSET
5, 4, 8, 9
ISEN1N to ISEN4N Negative Current Sense Input of Channel 1, 2, 3 and 4 for VDD Controller.
ISEN1P to ISEN4P Positive Current Sense Input of Channel 1, 2, 3 and 4 for VDD Controller.
6, 3, 7, 10
VDD Controller Voltage Sense Input. This pin is connected to the terminal
of VDD controller output voltage.
11
VSEN
Output Voltage Feedback Input of VDD Controller. This pin is the negative
input of the error amplifier for the VDD controller.
12
13
FB
COMP
RGND
Error Amplifier Output Pin of the VDD Controller.
Return Ground of VDD and VDDNB Controller. This pin is the common
negative input of output voltage differential remote sense for VDD and
VDDNB controllers.
14
15
16
17
18
Current Monitor Output for the VDD Controller. This pin outputs a voltage
proportional to the output current.
IMON
V064
Fixed 0.64V Reference Voltage Output. This voltage is only used to offset
the output voltage of IMON pin and IMONA pin. Connect a 0.47μF
capacitor from this pin to GND.
Current Monitor Output for the VDDNB Controller. This pin outputs a
voltage proportional to the output current.
IMONA
VDDIO
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
System Power Good Input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
19
PWROK
20
21
22
23
24
SVC
SVD
SVT
Serial VID Clock Input from Processor.
Serial VID Data input from Processor. This pin is a serial data line.
Serial VID Telemetry Input from VR. This pin is a push-pull output.
Over Clocking Offset Setting for the VDD Controller.
OFS
OFSA
Over Clocking Special Purpose Offset Setting for the VDDNB Controller.
OCP_TDC threshold setting individually for VDD and VDDNB controllers
and also the internal ramp slew rate setting (RSET and RSETA)
individually for VDD and VDDNB controllers
25
26
SET1
SET2
Quick response threshold setting individually for VDD and VDDNB
controllers (QRTH and QRTHA) and also the OCP_TDC trigger delay time
setting for both controllers and over clocking offset enable setting.
Over Current Indicator for Dual OCP Mechanism. This pin is an open drain
output.
27
28
OCP_L
VCC
Controller Power Supply Input. Connect this pin to 5V with an 1μF or
greater ceramic capacitor for decoupling.
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8877C-00 November 2012
www.richtek.com
3
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
