Datasheet > VcoreCont> RT8877C

RT8877C

更新时间： 2024-02-12 16:32:50

品牌	Logo	应用领域
立锜 - RICHTEK		控制器
页数	文件大小	规格书
38页	687K
描述
Dual-Output PWM Controller for AMD SVI2 CPU Power Supply

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技术参数
数据手册

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RT8877C 技术参数

Status：	Active	VID Table Support：	SVI2
Number of Phases：	2;4	Vcc (typ) (V)：	5
Vin (min) (V)：	10.8	Vin (max) (V)：	13.2
Accuracy (Vout>=1V) (+/- %)：	0.5	Freq (typ) (kHz)：
Built-in DAC Generator：	Yes	Number of MOSFET Drivers：
Features：	Diode Emulation Mode;Fast Transient Response;G-NAVP Control;OCP;OVP;Power Good;UVP	Package Type：	WQFN6x6-52

RT8877C 数据手册

RT8877C

Operation

Error Amp

MUX and ADC

Error amplifier generates COMP/COMPA signal by the

difference between VSET/VSETAand FB/FBA.

The MUX supports the inputs from SET1, SET2, OFS,

OFSA, IMON, IMONA, VSEN, or VSENA. The ADC

converts these analog signals to digital codes for reporting

or performance adjustment.

Offset cancellation

This block cancels the output offset voltage from voltage

ripple and current ripple to achieve accurate output voltage.

SVI2 Interface

The SVI2 interface uses SVC, SVD, and SVT pins to

communicate with CPU. RT8877C's performance and

behavior can be adjusted by commands sent by CPU or

platform.

PWM CMPx

The PWM comparator compares COMP signal and current

feedback signal to generate a signal for TONGENx.

TONGEN/TONGENA

UVLO

This block generates an on-time pulse which high interval

is based on the on-time setting and current balance.

The UVLO detects DVD and VCC pin voltages for under

voltage lockout protection and power on reset operation.

Current Balance

Loop Control Protection Logic

Per-phase current is sensed and adjusted by adjusting

on-time of each phase to achieve current balance for each

phase.

Loop control protection logic detects ENand UVLO signals

to initiate soft-start function and control PGOOD,

PGOODA and OCP_L signals after soft-start is finished.

When OCP event is triggered, the OCP_L pin voltage will

be pulled low.

OC/OV/UV/NV

VSEN/VSENA and output current are sensed for over

current, over voltage, under voltage, and negative voltage

protection.

DAC

The DAC receives VID codes from the SVI2 control logic

to generate an internal reference voltage (VSET/VSETA)

for controller.

RSET/RSETA

The Ramp generator is designed to improve noise immunity

and reduce jitter.

Soft-Start and Slew-Rate Control

This block controls the slew rate of the internal reference

voltage when output voltage changes.

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS8877C-00 November 2012

1...3 4 567 8 9...38

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