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RPC564L60L5CFQY PDF预览

RPC564L60L5CFQY

更新时间: 2024-12-02 00:38:15
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
137页 2426K
描述
microcontroller for Aerospace and Defense, SIL3/ASILD safety applications

RPC564L60L5CFQY 数据手册

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RPC56EL60L5  
32-bit Power Architecture® microcontroller  
for Aerospace and Defense, SIL3/ASILD safety applications  
Datasheet - production data  
– Power management unit (PMU)  
– Cyclic redundancy check (CRC) unit  
LQFP144 (20 x 20 x 1.4 mm)  
Decoupled Parallel mode for high-performance  
use of replicated cores  
Nexus Class 3+ interface  
Features  
GPIOs individually programmable as input,  
High-performance e200z4d dual core  
32-bit Power Architecture® technology CPU  
Core frequency as high as 120 MHz  
Dual issue five-stage pipeline core  
Variable Length Encoding (VLE)  
output or special function  
Three 6-channel general-purpose eTimer units  
2 FlexPWM units: 4 16-bit channels per module  
Communications interfaces  
– 2 LINFlexD channels  
Memory Management Unit (MMU)  
– 3 DSPI channels  
4 KB instruction cache with error detection  
– 2 FlexCAN interfaces (2.0B Active)  
– FlexRay module (V2.1 Rev. A)  
code  
Signal processing engine (SPE)  
Memory available  
Two 12-bit analog-to-digital converters (ADCs)  
– 1 MB flash memory with ECC  
– 16 input channels  
– 128 KB on-chip SRAM with ECC  
– Programmable CTU to synchronize ADCs  
conversion with timer and PWM  
– Built-in RWW capabilities for EEPROM  
emulation  
Sine wave generator (D/A with low pass filter)  
Single 3.0 V to 3.6 V voltage supply  
SIL3/ASILD innovative safety concept:  
LockStep mode and Fail-safe protection  
Ambient temperature range –40 °C to 125 °C  
Junction temperature range –40 °C to 150 °C  
– Sphere of replication (SoR) for key  
components (such as CPU core, eDMA,  
crossbar switch)  
Aerospace and Defense features  
– FCCU, interrupt controller  
– Dedicated traceability and part marking  
– Redundancy control and checker unit  
(RCCU) on outputs of the SoR connected  
to FCCU  
– Production parts approval documents  
available  
– Adapted Extended life time and  
obsolescence management  
– Boot-time Built-In Self-Test for Memory  
(MBIST) and Logic (LBIST) triggered by  
hardware  
– Extended Product Change Notification  
process  
– Boot-time Built-In Self-Test for ADC and  
flash memory triggered by software  
– Designed and manufactured to meet sub  
ppm quality goals  
– Replicated safety enhanced watchdog  
– Replicated junction temperature sensor  
– Non-maskable interrupt (NMI)  
– Advanced mold and frame designs for  
Superior resilience to harsh environment  
(acceleration, EMI, thermal, humidity)  
– 16-region memory protection unit (MPU)  
– Clock monitoring units (CMU)  
– Single Fabrication, Assembly and Test site  
– Dual internal production source capability  
September 2014  
DocID026934 Rev 1  
1/137  
This is information on a product in full production.  
www.st.com  

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