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RM73B2AT104J PDF预览

RM73B2AT104J

更新时间： 2024-11-27 01:22:39
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
16页 556K
描述
RF LDMOS Wideband Integrated Power Amplifier

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RM73B2AT104J 数据手册

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Document Number: MHVIC915NR2  
Rev. 9, 5/2006  
Freescale Semiconductor  
Technical Data  
RF LDMOS Wideband Integrated  
Power Amplifier  
The MHVIC915NR2 wideband integrated circuit is designed with on-chip  
matching that makes it usable from 750 to 1000 MHz. This multi-stage  
structure is rated for 26 to 28 Volt operation and covers all typical cellular base  
station modulation formats.  
MHVIC915NR2  
Final Application  
• Typical Single-Carrier N-CDMA Performance: VDD = 27 Volts, IDQ1  
=
746-960 MHz, 15 W, 27 V  
SINGLE N-CDMA, GSM/GSM EDGE  
RF LDMOS WIDEBAND  
80 mA, IDQ2 = 120 mA, Pout = 34 dBm, Full Frequency Band (746 to  
960 MHz), IS-95 CDMA (Pilot, Sync, Paging, Traffic Codes 8 Through 13)  
Power Gain — 31 dB  
Power Added Efficiency — 21%  
ACPR @ 750 kHz Offset — -50 dBc in 30 kHz Bandwidth  
INTEGRATED POWER AMPLIFIER  
Driver Applications  
• Typical Single-Carrier N-CDMA Performance: VDD = 27 Volts, IDQ1 = 80  
mA, IDQ2 = 120 mA, Pout = 23 dBm, Full Frequency Band (869-  
894 MHz), IS-95 CDMA (Pilot, Sync, Paging, Traffic Codes 8 Through 13),  
Channel Bandwidth = 1.2288 MHz. PAR = 9.8 dB @ 0.01%  
Probability on CCDF.  
16  
1
CASE 978-03  
PFP-16  
PLASTIC  
Power Gain — 31 dB  
Power Added Efficiency — 21%  
ACPR @ 750 kHz Offset — -60 dBc in 30 kHz Bandwidth  
ACPR @ 1.98 MHz Offset — -66 dBc in 30 kHz Bandwidth  
• Typical GSM Performance: VDD = 26 Volts, Pout = 15 W P1dB, Full  
Frequency Band (921-960 MHz)  
Power Gain — 30 dB @ P1dB  
Power Added Efficiency = 56% @ P1dB  
• Capable of Handling 3:1 VSWR, @ 27 Vdc, 880 MHz, 15 Watts CW  
Output Power  
• Characterized with Series Equivalent Large-Signal Impedance Parameters  
• On-Chip Matching (50 Ohm Input, DC Blocked, >9 Ohm Output)  
• Integrated Quiescent Current Temperature Compensation with  
Enable/Disable Function  
• On-Chip Current Mirror gm Reference FET for Self Biasing Application (1)  
• Integrated ESD Protection  
• RoHS Compliant  
• In Tape and Reel. R2 Suffix = 1,500 Units per 16 mm, 13 inch Reel.  
V
N.C.  
1
2
3
4
N.C.  
RD1  
16  
15  
14  
13  
V
RG1  
V
DS2  
/RF  
/RF  
/RF  
/RF  
/RF  
/RF  
V
RD1  
out  
out  
out  
out  
out  
out  
V
DS2  
V
RG1  
V
DS1  
2 Stage IC  
V
DS1  
V
DS2  
GND  
5
6
7
8
V
12  
11  
10  
9
DS2  
V
DS2  
RF  
in  
V
DS2  
/RF  
RF  
in  
out  
V
GS1  
V
DS2  
V
GS2  
N.C.  
V
V
GS1  
Quiescent Current  
Temperature Compensation  
(Top View)  
GS2  
Note: Exposed backside flag is source  
terminal for transistors.  
Figure 1. Block Diagram  
Figure 2. Pin Connections  
1. Refer to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to http://www.freescale.com/rf.  
Select Documentation/Application Notes - AN1987.  
© Freescale Semiconductor, Inc., 2006. All rights reserved.  
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