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RC82573E/SNA PDF预览

RC82573E/SNA

更新时间: 2024-11-15 15:49:19
品牌 Logo 应用领域
英特尔 - INTEL 局域网外围集成电路
页数 文件大小 规格书
39页 496K
描述
LAN Controller, PBGA196

RC82573E/SNA 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:BGA, BGA196,14X14,40Reach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
JESD-30 代码:S-PBGA-B196端子数量:196
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC封装代码:BGA
封装等效代码:BGA196,14X14,40封装形状:SQUARE
封装形式:GRID ARRAY电源:1.2,2.5,3.3 V
认证状态:Not Qualified子类别:Serial IO/Communication Controllers
表面贴装:YES温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOMuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1

RC82573E/SNA 数据手册

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82573 Family of GbE Controllers  
Datasheet  
Product Features  
„ PCIe*  
— x1 PCIe* interface on ICH7 or MCH devices  
„ Manageability  
— Intel® Active Management Technology (Intel®  
AMT) support (82573E only)  
— Peak bandwidth: 2 Gb/s per direction  
— Power management  
— High bandwidth density per pin  
— Alerting Standards Format 2.0 and advanced  
pass through support (82573E/V only)  
— Boot ROM Preboot eXecution Environment  
(PXE) Flash interface support  
„ MAC  
— Optimized transmit and receive queues  
— IEEE 802.3x compliant flow control with  
software controlled pause times and threshold  
values  
— Compliance with PCI Power Management 1.1  
and Advanced Configuration and Power  
Interface (ACPI) 2.0 register set compliant  
— Wake on LAN support  
— Caches up to 64 packet descriptors per queue  
— Programmable host memory receive buffers  
(256 bytes to 16 KB) and cache line size (16  
bytes to 256 bytes)  
„ Additional  
— Three activity and link indication outputs that  
directly drive LEDs  
— Programmable LEDs  
— 32 KB configurable transmit and receive FIFO  
— Internal PLL for clock generation that can use  
buffer  
a 25 MHz crystal  
— Mechanism available for reducing interrupts  
generated by transmit and receive operation  
— Descriptor ring management hardware for  
transmit and receive  
— Power saving feature for the 82573L. During  
the L1 and L2 link states, the 82573L asserts  
the Clock Request signal (CLKREQ#) to  
indicate that its PCIe* reference clock can be  
gated  
— Optimized descriptor fetching and write-back  
mechanisms  
— On-chip power control circuitry  
— Loopback capabilities  
— Wide, pipelined internal data path architecture  
„ PHY  
— JTAG (IEEE 1149.1) Test Access Port (TAP)  
— Integrated PHY for 10/100/1000 Mb/s full and  
built in silicon  
half duplex operation  
„ Technology  
— IEEE 802.3ab auto negotiation support  
— IEEE 802.3ab PHY compliance and  
compatibility  
— Lead-free 196-pin Thin and Fine Pitch Ball Grid  
Array (TF-BGA) package  
— Operating temperature: 0° C to 70° C (with  
external regulators)  
— DSP architecture implements digital  
adaptive equalization, echo cancellation,  
and cross-talk cancellation  
— Operating temperature: 0° to 55° C (with on-  
die 2.5V regulator)  
— Storage temperature -40° C to 125° C  
„ Host Offloading  
— Transmit and receive IP, TCP and UDP  
checksum off-loading capabilities  
— Transmit TCP segmentation, IPv6 offloading,  
and advanced packet filtering  
— IEEE 802.1q VLAN support with VLAN tag  
insertion, stripping and packet filtering for up  
to 4096 VLAN tags  
— Descriptor ring management hardware for  
transmit and receive  
Order Number: 315514-002  
Revision 2.5  

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