Datasheet
R01DS0053EJ0330
Rev. 3.30
RL78/G14
RENESAS MCU
Aug 12, 2016
True Low Power Platform (as low as 66 μA/MHz, and 0.60 μA for RTC + LVD), 1.6 V to 5.5 V operation,
16 to 512 Kbyte Flash, 44 DMIPS at 32 MHz, for General Purpose Applications
1. OUTLINE
1.1
Features
Ultra-Low Power Consumption Technology
• VDD = single power supply voltage of 1.6 to 5.5 V which
can operate a 1.8 V device at a low voltage
• HALT mode
• STOP mode
• SNOOZE mode
Event Link Controller (ELC)
• Event signals of 19 to 26 types can be linked to the
specified peripheral function.
Serial Interfaces
• CSI: 3 to 8 channels
• UART/UART (LIN-bus supported): 3 or 4 channels
• I2C/simplified I2C: 3 to 8 channels
RL78 CPU Core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed
from high speed (0.03125 μs: @ 32 MHz operation with
high-speed on-chip oscillator) to ultra-low speed (30.5
μs: @ 32.768 kHz operation with subsystem clock)
• Multiply/divide/multiply & accumulate instructions are
supported.
• Address space: 1 MB
• General-purpose registers: (8-bit register × 8) × 4 banks
• On-chip RAM: 2.5 to 48 KB
Timer
• 16-bit timer: 8 to 12 channels
(Timer Array Unit (TAU): 4 to 8 channels, Timer RJ: 1
channel, Timer RD: 2 channels, Timer RG: 1 channel)
• 12-bit interval timer: 1 channel
• Real-time clock: 1 channel (calendar for 99 years, alarm
function, and clock correction function)
• Watchdog timer: 1 channel (operable with the dedicated
low-speed on-chip oscillator)
A/D Converter
Code Flash Memory
• 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V)
• Analog input: 8 to 20 channels
• Internal reference voltage (1.45 V) and temperature
sensor
• Code flash memory: 16 to 512 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security
function)
D/A Converter
• On-chip debug function
• 8-bit resolution D/A converter (VDD = 1.6 to 5.5 V)
• Analog output: None or up to two channels
• Output voltage: 0 V to VDD
• Self-programming (with boot swap function/flash shield
window function)
Data Flash Memory
• Real-time output function
• Data flash memory: 4 KB and 8 KB
• Back ground operation (BGO): Instructions can be
executed from the program memory while rewriting the
data flash memory.
• Number of rewrites: 1,000,000 times (TYP.)
• Voltage of rewrites: VDD = 1.8 to 5.5 V
Comparator
• None or up to two channels
• Operating modes: Comparator high-speed mode,
comparator low-speed mode, window mode
• The external reference voltage or internal reference
voltage can be selected as the reference voltage.
High-speed On-chip Oscillator
• Select from 64 MHz, 48 MHz, 32 MHz, 24 MHz, 16 MHz,
12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and
1 MHz
• High accuracy: ±1.0% (VDD = 1.8 to 5.5 V, TA = -20 to
+85°C
I/O Port
• I/O port: 26 to 92 (N-ch open drain I/O [withstand
voltage of 6 V]: 2 to 4, N-ch open drain I/O [VDD
withstand voltage/EVDD withstand voltage]: 10 to 28)
• Can be set to N-ch open drain, TTL input buffer, and on-
chip pull-up resistor
Operating Ambient Temperature
• TA = -40 to +85°C (A: Consumer applications, D:
Industrial applications)
• Different potential interface: Can connect to a 1.8/2.5/3
V device
• On-chip key interrupt function
• TA = -40 to +105°C (G: Industrial applications)
• On-chip clock output/buzzer output controller
Power Management and Reset Function
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and
reset from 14 levels)
Others
• On-chip BCD (binary-coded decimal) correction circuit
Remark
The functions mounted depend on the product.
See 1.6 Outline of Functions.
Data Transfer Controller (DTC)
• Transfer modes: Normal transfer mode, repeat transfer
mode, block transfer mode
• Activation sources: Activated by interrupt sources.
• Chain transfer function
R01DS0053EJ0330 Rev. 3.30
Aug 12, 2016
Page 1 of 208
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