R5105N Series
Compact Watchdog Timer with VD
The R5105N Series are CMOS-based system power ICs with a voltage detector (VD) and watchdog timer (WDT) integrated in a single
chip. R5105N monitors the power system of devices equipped with microprocessors and prevents system runaway with a reset
signal when a malfunction occurs. The output delay time of the VD and watchdog timeout period/reset time can be adjusted high
accuracy with an external capacitor.
FEATURES
• Supply Current (ISS) ························Typ. 11μA (VDD=-VDET+0.5V,
Clock pulse input)
• Operating Voltage Range (VDD) ······0.9V to 6.0V
(VD Section)
• Output Delay Time (tPLH)················· Typ. 370ms (CD=0.1μF)
<
• Output Delay Time Accuracy·········· ± 16% (-40°C Topt 105°C)
=
=
(WDT Section)
• Watchdog Timeout Period (tWD)······ Typ. 310ms (CTW=0.1μF)
•
•
•
Detector Threshold Range (-VDET
Detector Threshold Accuracy ··········± 1%
Temp. coeff. of Detector Threshold ···Typ. ± 100ppm/°C
)
···1.5V to 5.5V (internally fixed)
• Reset Hold Time of WDT (tWR) ······· Typ. 34ms (CTW=0.1μF)
<
•
Watchdog Timeout Period Accuracy···· ± 33% (-40°C Topt 105°C)
• Package ········································· SOT-23-6
=
=
°
°
°
(The above shows specification at Topt=25 C. Design assurance value at -40 C
Topt
105 C is also available. For details, please refer to the datasheet.)
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=
BLOCK DIAGRAMS
TYPICAL APPLICATION
R5105Nxx1A
R5105Nxx1C
(Nch. open drain output)
(CMOS output)
Power Supply
Microprocessor
VDD
3
6
3
6
VDD
CD
VDD
CD
R
3
6
VDD
RESETB
R5105Nxx1A
4
1
RESET
I/O
Vref2
Vref2
Vref1
Vref1
5
1
5
1
GND
SCK
GND
SCK
2
4
2
4
CTW
CTW
Series
SCK
WATCHDOG
TIMER
CLOCK
DETECTOR
WATCHDOG
TIMER
CLOCK
DETECTOR
CD
CTW
2
GND
5
CD
CTW
RESETB
RESETB
SELECTION GUIDE
.
xx.
: Specify the detector threshold within the range 1.5V (
in 0.1V steps.
.
15
.
)
to 5.5V
(.
55
.
)
Package
Quantity per Reel
Part No.
SOT-23-6
3,000 pcs
R5105N
.
xx.
1.
∗-TR-F
: Select the output type from (
.
A
.
) Nch. open drain or (
.
C
.
) CMOS.
.
∗
PACKAGE (Top View)
TIMING CHART
SOT-23-6
6
5
4
+VDET
V
DD
-VDET
tPHL
tPHL
V
V
CD
+VTCD
-VTCD
1
2
3
tWD
tWDI
Vref2H
1
2
SCK
CTW
VDD
Watchdog timer clock input pin
CTW
Ext. Cap. pin for setting reset and
watchdog timeout period of WDT
Power supply pin
Vref2L
3
4
5
RESETB Output pin for Reset "L" signal
tPLH
tPLH
GND
Ground pin
V
SCK
Ext. Cap. pin for setting output
delay time of VD
6
CD
tWR
V
RESETB
APPLICATION
∗tPHL : Output delay time
∗tWDI : tWD/10 (SCK pulses input during this period are ignored.)
• Monitoring of the power system of devices equipped with microprocessors
No.EK-159-091101
CMOS Microprocessor Supervisory