Datasheet > QL16X24B-0PF100M

QL16X24B-0PF100M

更新时间： 2024-11-22 23:30:39

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QL16X24B-0PF100M 数据手册

QL16x24B

pASIC^®1 Family

Very-High-Speed CMOS FPGA

Rev C

pASIC

HIGHLIGHTS

Very High Speed – ViaLink metal-to-metal programmable–via

antifuse technology, allows counter speeds over 150 MHz and logic

cell delays of under 2 ns.

High Usable Density – A 16-by-24 array of 384 logic cells

provides 4,000 usable ASIC gates (7,000 PLD gates) in 84-pin

PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA and 160-pin

CQFP packages.

…4,000

usable ASIC gates,

122 I/O pins

Low-Power, High-Output Drive – Standby current typically 2 mA.

A 16-bit counter operating at 100 MHz consumes less than 50 mA.

Minimum IOL of 12 mA and IOH of 8 mA

Low-Cost, Easy-to-Use Design Tools – Designs entered and

simulated using QuickLogic's new QuickWorks development

environment, or with third-party CAE tools including Viewlogic,

Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place

and route on PC and workstation platforms using QuickLogic

software.

QL16x24B

Block Diagram

384 Logic Cells

Up to 114 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells

4-21

12 3 4 5 6 7...10

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