Datasheet > PVHT

PVHT

更新时间： 2024-11-25 01:24:55

品牌	Logo	应用领域
威世 - VISHAY		/
页数	文件大小	规格书
6页	89K
描述
High Stability - Very High Temperature (270 Â°C) Thin Film Wraparound Chip Resistors, Sulfur Resistant

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PVHT 数据手册

PVHT

Vishay Sfernice

www.vishay.com

High Stability - Very High Temperature (270 °C)

Thin Film Wraparound Chip Resistors, Sulfur Resistant

FEATURES

• Operating temperature range: -55 °C; +250 °C

• Storage temperature: -55 °C; +270 °C

• Gold terminations (< 1 μm thick)

• 5 sizes available (0402, 0603, 0805, 1206,

2010); other sizes upon request

• Temperature coefficient down to 5 ppm/°C

typical, 10 ppm/°C maximum (-55 °C; +270 °C)

• Tolerance down to 0.05 %

INTRODUCTION

• Load life stability: 0.8 % typical (1 % max.) after 2000 h at

250 °C (ambient) at Pn

For applications such as down hole applications, the need

for parts able to withstand very severe conditions

(temperature as high as 250 °C powered or up to 270 °C

un-powered) has led Vishay Sfernice to push out the limit of

the thin film technology.

• Shelf life stability: 1.5 % typical after 8000 h

• SMD wraparound

• 0.02 % upon request

Designers might read the application note “Power

Dissipation Considerations in High Precision Vishay

Sfernice Thin Film Chip Resistors and Arrays

(P, PRA etc…) (High Temperature Application)”

www.vishay.com/doc?53047 in conjunction with this

datasheet to help them to properly design their board and

get the best performances of the PVHT.

• TCR remains constant after long term storage at 270 °C

• Sulfur resistant (per ASTM B809-95 humid vapor test)

• Material categorization: for definitions of compliance

please see www.vishay.com/doc?99912

Vishay Sfernice research and development engineers will be

willing to support any customer design considerations.

STANDARD ELECTRICAL SPECIFICATIONS

RESISTANCE

RANGE

RATED POWER ⁽¹⁾⁽²⁾

LIMITING ELEMENT

TEMPERATURE

COEFFICIENT ⁽³⁾

ppmꢁ°C

TOLERANCE

ꢀ

MODEL

SIZE

P_{250 °C}

VOLTAGE

PVHT0402 0402

PVHT0603 0603

PVHT0805 0805

PVHT1206 1206

PVHT2010 2010

39 to 45K

39 to 108K

39 to 240K

39 to 900K

39 to 2.5M

0.031

0.062

0.100

0.165

0.2

0.05, 0.1, 0.5, 1

5, 10, 15, 25, 30, 50, 55

150

200

300

Notes

(1)

For power handling improvement, please refer to application note 53047 “Power Dissipation Considerations in High Precision Vishay

Sfernice Thin Film Chip Resistors and Arrays (High Temperature Applications)” www.vishay.com/doc?/53047 and consult Vishay Sfernice

See derating curve on next page

See Table 1 on next page

(2)

(3)

CLIMATIC SPECIFICATIONS

MECHANICAL SPECIFICATIONS

Substrate

Alumina

Operating temperature range

-55 °C; +250 °C

Resistive Element

Passivation

Protection

Thin Film

Silicon nitride (Si₃N₄)

Epoxy + Silicone

Storage temperature range

-55 °C; +270 °C

Terminations

Gold (< 1 μm) over nickel barrier

PERFORMANCE VS. HUMID SULFUR VAPOR

Caution:

50 °C 2 °C, 85 % 4 % RH,

Test conditions

exposure time 500 h

Performances obtained with following mounting conditions:

• Test board material: alumina

Resistance drift < (0.05 % R + 0.05 Ω),

Test results

no corrosion products observed

• Solder paste: PbSnAg (93.5/5/1.5)

Revision: 13-Nov-15

Document Number: 53060

For technical questions, contact: sferthinfilm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

12 3 4 5 6

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