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PSD913F2-A-70J PDF预览

PSD913F2-A-70J

更新时间: 2024-11-20 23:09:27
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
94页 472K
描述
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

PSD913F2-A-70J 数据手册

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PSD913F2  
PSD934F2 PSD954F2  
Flash In-System Programmable (ISP) Peripherals  
For 8-bit MCUs  
PRELIMINARY DATA  
FEATURES SUMMARY  
Single Supply Voltage:  
– 5 V±10% for PSD9xxF2  
– 3.3 V±10% for PSD9xxF2-V  
Figure 1. Packages  
Up to 2Mbit of Primary Flash Memory (8 uniform  
sectors)  
256Kbit Secondary Flash Memory (4 uniform  
sectors)  
Up to 256Kbit SRAM  
PQFP52 (T)  
Over 2,000 Gates of PLD: DPLD  
27 Reconfigurable I/O ports  
Enhanced JTAG Serial Port  
Programmable power management  
High Endurance:  
– 100,000 Erase/Write Cycles of Flash Memory  
– 1,000 Erase/Write Cycles of PLD  
PLCC52 (K)  
January 2002  
1/3  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  

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