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PSD913F2-70J PDF预览

PSD913F2-70J

更新时间: 2024-11-17 23:06:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 并行IO端口微控制器和处理器外围集成电路
页数 文件大小 规格书
94页 472K
描述
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

PSD913F2-70J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:PLASTIC, LCC-52
针数:52Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.8最长访问时间:7e-8 ns
JESD-30 代码:S-PQCC-J52JESD-609代码:e0
长度:19.1262 mmI/O 线路数量:27
端口数量:4端子数量:52
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC52,.8SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
ROM大小(位):1310720 Bits座面最大高度:4.57 mm
最大待机电流:0.0002 A子类别:Other Microprocessor ICs
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED紫外线可擦:N
宽度:19.1262 mmuPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches:1

PSD913F2-70J 数据手册

 浏览型号PSD913F2-70J的Datasheet PDF文件第2页浏览型号PSD913F2-70J的Datasheet PDF文件第3页浏览型号PSD913F2-70J的Datasheet PDF文件第4页浏览型号PSD913F2-70J的Datasheet PDF文件第5页浏览型号PSD913F2-70J的Datasheet PDF文件第6页浏览型号PSD913F2-70J的Datasheet PDF文件第7页 
PSD913F2  
PSD934F2 PSD954F2  
Flash In-System Programmable (ISP) Peripherals  
For 8-bit MCUs  
PRELIMINARY DATA  
FEATURES SUMMARY  
Single Supply Voltage:  
– 5 V±10% for PSD9xxF2  
– 3.3 V±10% for PSD9xxF2-V  
Figure 1. Packages  
Up to 2Mbit of Primary Flash Memory (8 uniform  
sectors)  
256Kbit Secondary Flash Memory (4 uniform  
sectors)  
Up to 256Kbit SRAM  
PQFP52 (T)  
Over 2,000 Gates of PLD: DPLD  
27 Reconfigurable I/O ports  
Enhanced JTAG Serial Port  
Programmable power management  
High Endurance:  
– 100,000 Erase/Write Cycles of Flash Memory  
– 1,000 Erase/Write Cycles of PLD  
PLCC52 (K)  
January 2002  
1/3  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  

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